ST7260 datasheet(99/117 Pages) STMICROELECTRONICS

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ST7260

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13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Notes:

1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2 and the sum of IIO (I/

O ports and control pins) must not exceed IVSS.

3. The RON pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,

not tested in production.

4. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIH

Input High Level Voltage

0.7xVDD

VDD

VIL

Input Low Voltage

VSS

0.3xVDD

Vhys

Schmitt trigger voltage hysteresis 1)

400

VOL

Output low level voltage 2)

VDD=5V

IIO=5 mA

0.8

IIO=7.5 mA

1.3

RON

Weak pull-up equivalent resistor 3)

VIN=VSS

VDD=5 V

100

Ω

tw(RSTL)out Generated reset pulse duration

External pin or

internal reset sources

1/fSFOSC

µs

th(RSTL)in External reset pulse hold time

µs

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