ICS1893AF datasheet(84/137 Pages) RENESAS

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ICS1893AF, Rev D 10/26/04

October, 2004

Chapter 8

Management Register Set

ICS1893AF Data Sheet - Release

8.11

Table 8-16 lists the bits for the Extended Control Register, which the ICS1893AF provides to allow an STA

to customize the operations of the device.

Note:

For an explanation of acronyms used in Table 8-16, see Chapter 1, “Abbreviations and Acronyms”.

During any write operation to any bit in this register, the STA must write the default value to all

Reserved bits.

† The default is the state of this pin at reset.

Table 8-16.

Extended Control Register (register 16 [0x10])

Bit

Definition

When Bit = 0

When Bit = 1

Ac-

cess

De-

fault

Hex

16.15

Command Override Write

enable

Disabled

Enabled

–

16.14

ICS reserved

Read unspecified

RW/0

–

16.13

ICS reserved

Read unspecified

RW/0

–

16.12

ICS reserved

Read unspecified

RW/0

–

16.11

ICS reserved

Read unspecified

RW/0

–

16.10

PHY Address Bit 4

For a detailed explanation of this bit’s operation,

see Section 6.5, “Status Interface”.

–

P4RD†

16.9

PHY Address Bit 3

For a detailed explanation of this bit’s operation,

see Section 6.5, “Status Interface”.

–

P3TD†

16.8

PHY Address Bit 2

For a detailed explanation of this bit’s operation,

see Section 6.5, “Status Interface”.

–

P2LI†

16.7

PHY Address Bit 1

For a detailed explanation of this bit’s operation,

see Section 6.5, “Status Interface”.

–

P1CL†

–

16.6

PHY Address Bit 0

For a detailed explanation of this bit’s operation,

see Section 6.5, “Status Interface”.

–

P0AC†

16.5

Stream Cipher Test Mode

Normal operation

Test mode

–

16.4

ICS reserved

Read unspecified

RW/0

–

16.3

NRZ/NRZI encoding

NRZ encoding

NRZI encoding

–

16.2

Transmit invalid codes

Disabled

Enabled

–

16.1

ICS reserved

Read unspecified

RW/0

–

16.0

Stream Cipher disable

Stream Cipher enabled Stream Cipher disabled

–

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