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ICS1893AF 数据表(PDF) 95 Page - Renesas Technology Corp |
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ICS1893AF 数据表(HTML) 95 Page - Renesas Technology Corp |
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95 / 137 page  Chapter 8 Management Register Set ICS1893AF, Rev. D 10/26/04 October, 2004 95 ICS1893AF Data Sheet - Release Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 8.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893AF from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted- Pair Receiver inputs. • One, the ICS1893AF 10Base-T Link Integrity Test state machine is forced into the ‘Link Passed’ state regardless of the Twisted-Pair Receiver input conditions. 8.13.9 Squelch Inhibit (bit 18.0) The Squelch Inhibit bit allows an STA to control the ICS1893AF Squelch Detection in 10Base-T mode. When an STA sets this bit to logic: • Zero, before the ICS1893AF can establish a valid link, the ICS1893AF must receive valid 10Base-T data. • One, before the ICS1893AF can establish a valid link, the ICS1893AF must receive both valid 10Base-T data followed by an IDL. |
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