ICS1893AFILF datasheet(21/137 Pages) RENESAS

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Chapter 5

Operating Modes Overview

ICS1893AF, Rev. D 10/26/04

October, 2004

ICS1893AF Data Sheet - Release

5.1.2.3

Software Reset

Entering Software Reset

Initiation of a software reset occurs when a management entity writes a logic one to Control Register bit

0.15. When this write occurs, the ICS1893AF enters the reset state for two REF_IN clock cycles.

Note:

Entering a software reset is nearly identical to entering a hardware reset or a power-on reset,

except that during a software-initiated reset, the ICS1893AF does not enter the power-down state.

Exiting Software Reset

At the completion of a reset (either hardware, power-on, or software), the ICS1893AF sets all registers to

their default values. This action automatically clears (that is, sets equal to logic zero) Control Register bit

0.15, the software reset bit. Therefore, for a software reset (only), bit 0.15 is a self-clearing bit that indicates

the completion of the reset process.

Note:

The RESETn pin is active low but Control Register bit 0.15 is active high.

Exiting a software reset is nearly identical to exiting a hardware reset or a power-on reset, except that

upon exiting a software-initiated reset, the ICS1893AF does not re-latch its Serial Management Port

Address into the Extended Control Register. [For information on the Serial Management Port Address,

see Section 8.11.3, “PHY Address (bits 16.10:6)”.]

The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit

that is used to initiate a software reset. During a hardware or power-on reset, Control Register bit 0.15

does not get set to logic one. As a result, this bit 0.15 cannot be used to indicate the completion of the

reset process for hardware or power-on resets.

5.2

Power-Down Operations

The ICS1893AF enters the power-down state whenever either (1) the RESETn pin is low or (2) Control

internal functions and drives all MAC/Repeater Interface output pins to logic zero except for those that

support the MII Serial Management Port. In addition, the ICS1893AF tri-states its Twisted-Pair Transmit

pins (TP_TXP and TP_TXN) to achieve an additional reduction in power.

There is one significant difference between entering the power-down state by setting Control Register bit

0.11 as opposed to entering the power-down state during a reset. When the ICS1893AF enters the

power-down state:

• By setting Control Register bit 0.11, the ICS1893AF maintains the value of all Management Register bits

except for the latching low (LL), latching high (LH), and latching maximum (LMX) status bits. Instead,

these LL, LH, and LMX Management Register bits are re-initialized to their default values.

• During a reset, the ICS1893AF sets all of its Management Register bits to their default values. It does not

maintain the state of any Management Register bit.

For more information on power-down operations, see the following:

• Section 8.14, “Register 19: Extended Control Register 2”

• Section 10.4, “DC Operating Characteristics”, which has tables that specify the ICS1893AF power

consumption while in the power-down state

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