PCF2104CUSLASH2 datasheet(6/56 Pages) MOTOROLA

6 / 56 page

1997 Dec 16

Philips Semiconductors

Product speciﬁcation

LCD controller/driver

PCF2104x

7.8

OSC: oscillator

When the on-chip oscillator is used, this pin must be

connected to VDD. An external clock signal, if used, is input

at this pin.

7.9

SCL: serial clock line

Input for the I2C-bus clock signal.

7.10

SDA: serial data line

Input/output for the I2C-bus data line.

7.11

SA0: address pin

The hardware sub-address line is used to program the

device sub-address for 2 different PCF2104xs on the

same I2C-bus.

7.12

T1: test pad

Must be connected to VSS. Not user accessible.

FUNCTIONAL DESCRIPTION (see Fig.1)

8.1

LCD bias voltage generator

The intermediate bias voltages for the LCD display are

also generated on-chip. This removes the need for an

external resistive bias chain and significantly reduces the

system power consumption. The optimum levels depend

on the multiplex rate and are selected automatically when

the number of lines in the display is defined.

The optimum value of VOP depends on the multiplex rate,

the LCD threshold voltage (Vth) and the number of bias

levels. The relationships are given in Table 1.

Using a 5-level bias scheme for 1 : 16 MUX rate allows

VOP < 5 V for most LCD liquids. The effect on the display

contrast is negligible.

Table 1

Optimum values for VOP

MUX

RATE

NUMBER

OF BIAS

LEVELS

VOP/Vth

DISCRIMINATION

Von/Voff

1 : 16

3.67

1.277

1 : 32

5.19

1.196

8.2

Oscillator

The on-chip oscillator provides the clock signal for the

display system. No external components are required.

Pin OSC must be connected to VDD.

8.3

External clock

If an external clock is to be used, it must be input at

pin OSC. The resulting display frame frequency is given by

fframe = 1⁄2304fosc. A clock signal must always be present,

otherwise the LCD may be frozen in a DC state.

8.4

Power-on reset

The Power-on reset block initializes the chip after

power-on or power failure.

8.5

Registers

The PCF2104x has two 8-bit registers, an instruction

signal (RS) determines which register will be accessed.

The instruction register stores instruction codes such as

display clear and cursor shift, and address information for

the Display Data RAM (DDRAM) and Character Generator

RAM (CGRAM). The instruction register can be written to,

but not read from, by the system controller.

The data register temporarily stores data to be read from

the DDRAM and CGRAM. When reading, data from the

DDRAM or CGRAM (corresponding to the address in the

Address Counter) is written to the data register prior to

being read by the ‘Read data’ instruction.

8.6

Busy Flag

The Busy Flag indicates the free/busy status of the

PCF2104x. Logic 1 indicates that the chip is busy and

further instructions will not be accepted. The Busy Flag is

output at pin DB7 when RS = logic 0 and R/W = logic 1.

Instructions should only be written after checking that the

Busy Flag is at logic 0 or waiting for the required number

of clock cycles.

PCF2104CU/2 数据表(PDF) 6 Page - Motorola, Inc

PCF2104CU/2 数据表(HTML) 6 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载