TMPR4955AF datasheet(49/168 Pages) TOSHIBA

49 / 168 page

開発中

Chapter 2 Features

2-5

Table 2.2.4 Interrupt Interface

PIN NAME

I / O

FUNCTION

Int(5:0)*

Interrupt

Six lines of general-purpose processor interrupt inputs, which are sampled at rising edges of the

Master Clock.

Note: Int(5)* can use when TintDis signal is “1”.

NMI*

Nonmaskable interrupt

Nonmaskable interrupt input, which is sampled at rising edges of the Master Clock.

Table 2.2.5 JTAG Interface

PIN NAME

I / O

FUNCTION

JTDI

JTAG data input / Debug interrupt input

Run-time mode: Input serial data to JTAG data/instruction registers.

Real-time mode: Interrupt input to change the debug unit state from real-time mode to run-time mode.

JTCK

JTAG clock input

Clock input for JTAG. The JTDI and JTMS data are latched on rising edges of this clock.

JTDO/TPC(0)

JTAG data output / Trace PC output

Data is serially shifted out from this pin. / Outputs a non-sequential program counter value

synchronously with DCLK.

JTMS

JTAG command

Controls mainly the status transition of the TAP controller state machine.

When the serial input data is a JTAG command, apply a high signal (= 1) to this pin.

DCLK

Debug clock (1/3 CPU clock)

Clock output for a real-time debug system. Timings of the serial monitor bus and PC trace interface

signals all are defined by this debug clock DCLK.

The TX4955A’s operating clock frequency is 1/3 that of Pclock. (Pclock is Internal CPU Clock)

PCST(8:0)

PC trace status

Outputs PC trace status information and serial monitor bus mode.

TPC(3:1) Note 1

Trace PC output

Outputs a non-sequential program counter value synchronously with DCLK.

TRST*

Test reset input

Reset input for a real-time debug system. When TRST* is asserted (= 0), the debug support unit (DSU)

is initialized. TRST* should be asserted when DSU is not used.

Note1: Leave TPC (3-1) pins open when not using them as PC trace outputs for debugging.

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