TMPR4955AF datasheet(7/168 Pages) TOSHIBA

7 / 168 page

TMPR4955A

Contents

Handling Precautions

TMPR4955A

Chapter 1. Introduction ............................................................................................................................ 1-1

1.1

Overview ........................................................................................................................................ 1-1

1.2

Notation used in this manual ....................................................................................................... 1-1

1.2.1

Numerical notation ................................................................................................................ 1-1

1.2.2

Data notation.......................................................................................................................... 1-1

1.2.3

Signal notation ....................................................................................................................... 1-1

1.2.4

Register notation.................................................................................................................... 1-1

Chapter 2. Features .................................................................................................................................. 2-1

2.1

Block Diagram ............................................................................................................................... 2-2

2.2

Pin Description .............................................................................................................................. 2-3

2.2.1

TX4955A pin out (160-pin QFP)............................................................................................ 2-3

Chapter 3. Initialization Interface........................................................................................................... 3-1

3.1

Functional Overview ..................................................................................................................... 3-1

3.1.1

System Coordination.............................................................................................................. 3-1

3.2

Reset Signal Description............................................................................................................... 3-2

3.2.1

Cold Reset ............................................................................................................................... 3-2

3.2.2

Warm Reset............................................................................................................................. 3-2

3.3

TX4955A......................................................................................................................................... 3-4

3.3.1

Power Modes (Doze/Halt Mode) ............................................................................................ 3-4

3.3.2

Operating Modes .................................................................................................................... 3-5

3.3.3

System Endianness ................................................................................................................ 3-5

3.3.4

Reverse Endianness ............................................................................................................... 3-6

3.3.5

Instruction Trace Support ..................................................................................................... 3-6

3.3.6

Bootstrap Exception Vector ................................................................................................... 3-6

3.3.7

Interrupt Enable .................................................................................................................... 3-6

3.3.8

Floating-Point Reigsters ........................................................................................................ 3-6

Chapter 4. Clock Interface........................................................................................................................ 4-1

4.1

Signal Terminology........................................................................................................................ 4-1

4.2

Basic System Clocks...................................................................................................................... 4-2

4.2.1

MasterClock............................................................................................................................ 4-2

4.2.2

PClock ..................................................................................................................................... 4-2

4.2.3

SClock ..................................................................................................................................... 4-2

4.2.4

PClock-to-SClock Division ..................................................................................................... 4-3

4.2.5

Phase-Locked Loop (PLL) ...................................................................................................... 4-3

4.3

Connecting Clocks to a Phase-Locked System ............................................................................ 4-4

Chapter 5 Cache Organization................................................................................................................ 5-1

5.1

Memory Organization ................................................................................................................... 5-1

5.2

Cache Organization....................................................................................................................... 5-2

5.2.1

Cache Sizes ............................................................................................................................. 5-2

5.2.2

Cache Line Lengths ............................................................................................................... 5-2

5.2.3

Organization of the Instruction Cache (I-Cache) ................................................................. 5-2

5.2.4

Instruction cache address field.............................................................................................. 5-3

5.2.5

Instruction cache configuration............................................................................................. 5-3

5.2.6

Organization of the Data Cache (D-Cache) .......................................................................... 5-4

5.2.7

Data cache address field ........................................................................................................ 5-4

5.2.8

Data cache configuration ....................................................................................................... 5-4

5.3

Lock function ................................................................................................................................. 5-5

5.3.1

Lock function .......................................................................................................................... 5-5

5.3.2

Operation during lock ............................................................................................................ 5-6

5.3.3

Example of Data cache locking..............................................................................................5-6

TMPR4955AF 数据表(PDF) 7 Page - Toshiba Semiconductor

TMPR4955AF 数据表(HTML) 7 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载