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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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TMPR4955AF 数据表(PDF) 58 Page - Toshiba Semiconductor |
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TMPR4955AF 数据表(HTML) 58 Page - Toshiba Semiconductor |
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58 / 168 page  Chapter 4 Clock Interface 4-2 4.2 Basic System Clocks The various clock signals used in the TX4955A processor are described below, starting with MasterClock MasterClock MasterClock MasterClock, upon which the processor bases all internal and external clocking. The clocks on the TX4955A processor are controlled by an on-processor Phase-locked Loop (PLL) circuit. This circuit keeps the TX4955A processor’s internal clock edges aligned with the clock edges of the MasterClock MasterClock MasterClock MasterClock signal, which itself acts as the master system clock. Inside the TX4955A processor, the MasterClock MasterClock MasterClock MasterClock signal can be multiplied by a factor set by the DivMode (1:0) DivMode (1:0) DivMode (1:0) DivMode (1:0) inputs to the processor. All internal clocks are then derived from this clock. The TX4955A processor has two primary internal clocks, the pipeline (also referred to as processor) clock, PClock PClock PClock PClock, and the system interface clock, SClock SClock SClock SClock. SClock SClock SClock SClock has the same frequency and phase as MasterClock MasterClock MasterClock MasterClock. 4.2.1 MasterClock The Processor bases all internal and external clocking on the single MasterClock MasterClock MasterClock MasterClock input signal. MasterClock MasterClock MasterClock MasterClock specifications are shown in Figure 4.2.1. tMCF tMCR tMCH tMCL tMCP 0.8VCC IO 0.2VCC IO Figure 4.2.1 MasterClock 4.2.2 PClock The pipeline (or processor) clock, PClock PClock PClock PClock, can be 2, 2.5, 3 or 4 times the MasterClock MasterClock MasterClock MasterClock frequency. This multiplication factor is determined by DivMode (1:0) DivMode (1:0) DivMode (1:0) DivMode (1:0) pins, which are static signal inputs to TX4955A. All internal registers and latches use PClock PClock PClock PClock. 4.2.3 SClock The system interface clock, SClock SClock SClock SClock, is the same as the MasterClock MasterClock MasterClock MasterClock frequency. SClock SClock SClock SClock is always derived from Pclock. Pclock. Pclock. Pclock. The TX4955A processor drives its outputs on this clock edge. The first rising edge of SClock SClock SClock SClock, after ColdReset ColdReset ColdReset ColdReset* is deasserted, is aligned with the first rising edge of MasterClock MasterClock MasterClock MasterClock. |
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