Data Sheet

ADRF5347

APPLICATION INFORMATION

analog.com

Rev. 0 | 13 of 15

The ADRF5347 has two power-supply pins (VDD and VSS) and

three control pins (V1, V2, and LS). Figure 25 shows the external

components and connections for the supply and control pins. The

VDD and VSS pins are decoupled with a 100 pF and 4.7 μF multilay-

er ceramic capacitors. The control pins V1 and V2 are decoupled

with 100 pF multilayer ceramic capacitors, while the LS control pin

can be left floating or tied to ground. The device pinout allows

to place the decoupling capacitors close to the device. No other

external components are needed for bias and operation, except DC

blocking capacitors on the RF pins when the RF lines are biased

at a voltage different than 0 V. For more details, see the Table 5

section.

Figure 25. Recommended Schematic

RECOMMENDATIONS FOR PCB DESIGN

The RF ports are matched to 50 Ω internally and the pinout is

designed to mate a coplanar waveguide (CPWG) with 50 Ω charac-

teristic impedance on the PCB. Figure 26 shows the referenced

CPWG RF trace design for an RF substrate with 10 mil thick

Rogers RO4350 dielectric material. An RF trace with 18 mil width

and 13 mil clearance is recommended for the 2.7 mil finished

copper thickness.

Figure 26. Example PCB Stack-Up

Figure 27 shows the routing of the RF traces, supply, and control

signals from the device. The ground planes are connected with as

many filled, through vias as allowed for optimal RF and thermal

performance. The primary thermal path for the device is the bottom

side.

Figure 27. PCB Routings

Figure 28 shows the recommended layout from the device RF pins

to the 50 Ω CPWG on the referenced stack-up. The ground pads

are drawn as solder mask defined and the signal pads are drawn

as pad defined. The RF trace from the PCB pad is extended with

the same width and tapered to the RF trace with a 45° angle.

The paste mask is also designed to match the pad without any

aperture reduction. The paste is divided into multiple openings for

the paddle.

Figure 28. Recommended RF Pin Transitions

For alternate PCB stack-ups with different dielectric thickness and

CPWG design, contact Analog Devices Technical Support for fur-

ther recommendations.