DSPIC30F datasheet(119/220 Pages) MICROCHIP

119 / 220 page

 2004 Microchip Technology Inc.

Preliminary

DS70116C-page 117

dsPIC30F5011/5013

18.0

DATA CONVERTER

INTERFACE (DCI) MODULE

18.1

Module Introduction

The dsPIC30F Data Converter Interface (DCI) module

allows simple interfacing of devices, such as audio

coder/decoders (Codecs), A/D converters and D/A

converters. The following interfaces are supported:

• Framed Synchronous Serial Transfer (Single or

Multi-Channel)

• Inter-IC Sound (I2S) Interface

• AC-Link Compliant mode

The DCI module provides the following general

features:

• Programmable word size up to 16 bits

• Support for up to 16 time slots, for a maximum

frame size of 256 bits

• Data buffering for up to 4 samples without CPU

overhead

18.2

Module I/O Pins

There are four I/O pins associated with the module.

When enabled, the module controls the data direction

of each of the four pins.

18.2.1

CSCK PIN

The CSCK pin provides the serial clock for the DCI

module. The CSCK pin may be configured as an input

or output using the CSCKD control bit in the DCICON2

SFR. When configured as an output, the serial clock is

provided by the dsPIC30F. When configured as an

input, the serial clock must be provided by an external

device.

18.2.2

CSDO PIN

The serial data output (CSDO) pin is configured as an

output only pin when the module is enabled. The

CSDO pin drives the serial bus whenever data is to be

transmitted. The CSDO pin is tri-stated or driven to ‘0’

during CSCK periods when data is not transmitted,

depending on the state of the CSDOM control bit. This

allows other devices to place data on the serial bus

during transmission periods not used by the DCI

module.

18.2.3

CSDI PIN

The serial data input (CSDI) pin is configured as an

input only pin when the module is enabled.

18.2.3.1

COFS PIN

The Codec frame synchronization (COFS) pin is used

to synchronize data transfers that occur on the CSDO

and CSDI pins. The COFS pin may be configured as an

input or an output. The data direction for the COFS pin

is determined by the COFSD control bit in the

DCICON1 register.

The DCI module accesses the shadow registers while

the CPU is in the process of accessing the memory

mapped buffer registers.

18.2.4

BUFFER DATA ALIGNMENT

Data values are always stored left justified in the buff-

ers since most Codec data is represented as a signed

2’s complement fractional number. If the received word

length is less than 16 bits, the unused LS bits in the

receive buffer registers are set to ‘0’ by the module. If

the transmitted word length is less than 16 bits, the

unused LS bits in the transmit buffer register are

ignored by the module. The word length setup is

described in subsequent sections of this document.

18.2.5

TRANSMIT/RECEIVE SHIFT

The DCI module has a 16-bit shift register for shifting

serial data in and out of the module. Data is shifted in/

out of the shift register MS bit first, since audio PCM

data is transmitted in signed 2’s complement format.

18.2.6

DCI BUFFER CONTROL

The DCI module contains a buffer control unit for trans-

ferring data between the shadow buffer memory and

the serial shift register. The buffer control unit is a sim-

ple 2-bit address counter that points to word locations

in the shadow buffer memory. For the receive memory

space (high address portion of DCI buffer memory), the

address counter is concatenated with a ‘0’ in the MSb

location to form a 3-bit address. For the transmit mem-

ory space (high portion of DCI buffer memory), the

address counter is concatenated with a ‘1’ in the MSb

location.

Note:

The

DCI

buffer

control

unit

always

accesses the same relative location in the

transmit and receive buffers, so only one

address counter is provided.

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