DSPIC30F datasheet(121/220 Pages) MICROCHIP

121 / 220 page

 2004 Microchip Technology Inc.

Preliminary

DS70116C-page 119

dsPIC30F5011/5013

18.3

DCI Module Operation

18.3.1

MODULE ENABLE

The DCI module is enabled or disabled by setting/

clearing the DCIEN control bit in the DCICON1 SFR.

Clearing the DCIEN control bit has the effect of reset-

ting the module. In particular, all counters associated

with CSCK generation, frame sync, and the DCI buffer

control unit are reset.

The DCI clocks are shutdown when the DCIEN bit is

cleared.

When enabled, the DCI controls the data direction for

the four I/O pins associated with the module. The Port,

LAT and TRIS register values for these I/O pins are

overridden by the DCI module when the DCIEN bit is set.

It is also possible to override the CSCK pin separately

when the bit clock generator is enabled. This permits

the bit clock generator to operate without enabling the

rest of the DCI module.

18.3.2

WORD SIZE SELECTION BITS

The WS<3:0> word size selection bits in the DCICON2

SFR determine the number of bits in each DCI data

word. Essentially, the WS<3:0> bits determine the

counting period for a 4-bit counter clocked from the

CSCK signal.

Any data length, up to 16-bits, may be selected. The

value loaded into the WS<3:0> bits is one less the

desired word length. For example, a 16-bit data word

size is selected when WS<3:0> = 1111.

18.3.3

FRAME SYNC GENERATOR

The frame sync generator (COFSG) is a 4-bit counter

that sets the frame length in data words. The frame

sync generator is incremented each time the word size

counter is reset (refer to Section 18.3.2). The period for

the frame synchronization generator is set by writing

the COFSG<3:0> control bits in the DCICON2 SFR.

The COFSG period in clock cycles is determined by the

following formula:

EQUATION 18-1:

COFSG PERIOD

Frame lengths, up to 16 data words, may be selected.

The frame length in CSCK periods can vary up to a

maximum of 256 depending on the word size that is

selected.

18.3.4

FRAME SYNC MODE

CONTROL BITS

The type of frame sync signal is selected using the

Frame

Synchronization

mode

control

bits

(COFSM<1:0>) in the DCICON1 SFR. The following

operating modes can be selected:

• Multi-Channel mode

•I2S mode

• AC-Link mode (16-bit)

• AC-Link mode (20-bit)

The operation of the COFSM control bits depends on

whether the DCI module generates the frame sync

signal as a master device, or receives the frame sync

signal as a slave device.

The master device in a DSP/Codec pair is the device

that generates the frame sync signal. The frame sync

signal initiates data transfers on the CSDI and CSDO

pins and usually has the same frequency as the data

sample rate (COFS).

The DCI module is a frame sync master if the COFSD

control bit is cleared and is a frame sync slave if the

COFSD control bit is set.

18.3.5

MASTER FRAME SYNC

OPERATION

When the DCI module is operating as a frame sync

master device (COFSD = 0), the COFSM mode bits

determine the type of frame sync pulse that is

generated by the frame sync generator logic.

A new COFS signal is generated when the frame sync

generator resets to ‘0’.

In the Multi-Channel mode, the frame sync pulse is

driven high for the CSCK period to initiate a data trans-

fer. The number of CSCK cycles between successive

frame sync pulses will depend on the word size and

frame sync generator control bits. A timing diagram for

the frame sync signal in Multi-Channel mode is shown

in Figure 18-2.

In the AC-Link mode of operation, the frame sync sig-

nal has a fixed period and duty cycle. The AC-Link

frame sync signal is high for 16 CSCK cycles and is low

for 240 CSCK cycles. A timing diagram with the timing

details at the start of an AC-Link frame is shown in

Figure 18-3.

In the I2S mode, a frame sync signal having a 50% duty

cycle is generated. The period of the I2S frame sync

signal in CSCK cycles is determined by the word size

and frame sync generator control bits. A new I2S data

transfer boundary is marked by a high-to-low or a

low-to-high transition edge on the COFS pin.

Note:

These WS<3:0> control bits are used only

in the Multi-Channel and I2S modes. These

bits have no effect in AC-Link mode since

the data slot sizes are fixed by the protocol.

Note:

The COFSG control bits will have no effect

in AC-Link mode since the frame length is

set to 256 CSCK periods by the protocol.

Frame Length = Word Length • (FSG Value + 1)

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