DSPIC30F datasheet(125/220 Pages) MICROCHIP

125 / 220 page

 2004 Microchip Technology Inc.

Preliminary

DS70116C-page 123

dsPIC30F5011/5013

18.3.16

TRANSMIT STATUS BITS

There are two transmit status bits in the DCISTAT SFR.

The TMPTY bit is set when the contents of the transmit

buffer registers are transferred to the transmit shadow

registers. The TMPTY bit may be polled in software to

determine when the transmit buffer registers may be

written. The TMPTY bit is cleared automatically by the

hardware when a write to one of the four transmit

buffers occurs.

The TUNF bit is read only and indicates that a transmit

underflow has occurred for at least one of the transmit

buffer registers that is in use. The TUNF bit is set at the

time the transmit buffer registers are transferred to the

transmit shadow registers. The TUNF status bit is

cleared automatically when the buffer register that

underflowed is written by the CPU.

18.3.17

RECEIVE STATUS BITS

There are two receive status bits in the DCISTAT SFR.

The RFUL status bit is read only and indicates that new

data is available in the receive buffers. The RFUL bit is

cleared automatically when all receive buffers in use

have been read by the CPU.

The ROV status bit is read only and indicates that a

receive overflow has occurred for at least one of the

receive buffer locations. A receive overflow occurs

when the buffer location is not read by the CPU before

new data is transferred from the shadow registers. The

ROV status bit is cleared automatically when the buffer

When a receive overflow occurs for a specific buffer

location, the old contents of the buffer are overwritten.

18.3.18

SLOT STATUS BITS

The SLOT<3:0> status bits in the DCISTAT SFR indi-

cate the current active time slot. These bits will corre-

spond to the value of the frame sync generator counter.

The user may poll these status bits in software when a

DCI interrupt occurs to determine what time slot data

was last received and which time slot data should be

loaded into the TXBUF registers.

18.3.19

CSDO MODE BIT

The CSDOM control bit controls the behavior of the

CSDO pin during unused transmit slots. A given trans-

mit time slot is unused if it’s corresponding TSEx bit in

the TSCON SFR is cleared.

If the CSDOM bit is cleared (default), the CSDO pin will

be low during unused time slot periods. This mode will

be used when there are only two devices attached to

the serial bus.

If the CSDOM bit is set, the CSDO pin will be tri-stated

during unused time slot periods. This mode allows mul-

tiple devices to share the same CSDO line in a multi-

channel application. Each device on the CSDO line is

configured so that it will only transmit data during

specific time slots. No two devices will transmit data

during the same time slot.

18.3.20

DIGITAL LOOPBACK MODE

Digital Loopback mode is enabled by setting the

DLOOP control bit in the DCISTAT SFR. When the

DLOOP bit is set, the module internally connects the

CSDO signal to CSDI. The actual data input on the

CSDI I/O pin will be ignored in Digital Loopback mode.

18.3.21

UNDERFLOW MODE CONTROL BIT

When an underflow occurs, one of two actions may

occur depending on the state of the Underflow mode

(UNFM) control bit in the DCICON2 SFR. If the UNFM

bit is cleared (default), the module will transmit ‘0’s on

the CSDO pin during the active time slot for the buffer

location. In this Operating mode, the Codec device

attached to the DCI module will simply be fed digital

‘silence’. If the UNFM control bit is set, the module will

transmit the last data written to the buffer location. This

Operating mode permits the user to send continuous

data to the Codec device without consuming CPU

overhead.

18.4

DCI Module Interrupts

The frequency of DCI module interrupts is dependent

on the BLEN<1:0> control bits in the DCICON2 SFR.

An interrupt to the CPU is generated each time the set

buffer length has been reached and a shadow register

transfer takes place. A shadow register transfer is

defined as the time when the previously written TXBUF

values are transferred to the transmit shadow registers

and new received values in the receive shadow

registers are transferred into the RXBUF registers.

Note:

The transmit status bits only indicate sta-

tus for buffer locations that are used by the

module. If the buffer length is set to less

than four words, for example, the unused

buffer locations will not affect the transmit

status bits.

Note:

The receive status bits only indicate status

for buffer locations that are used by the

module. If the buffer length is set to less

than four words, for example, the unused

buffer locations will not affect the transmit

status bits.

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