Preliminary Data Sheet

AD8196

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CABLE LENGTHS AND EQUALIZATION

The AD8196 offers two levels of programmable equalization

for the high speed inputs: 6 dB and 12 dB. The equalizer of

the AD8196 supports video data rates of up to 2.25 Gbps, and

as shown in Figure 14, it can equalize more than 20 meters of 24

AWG HDMI cable at 2.25Gbps, which corresponds to the video

format, 1080p with deep color.

The length of cable that can be used in a typical HDMI/DVI

application depends on a large number of factors including:

•

Cable quality: the quality of the cable in terms of conductor

wire gauge and shielding. Thicker conductors have lower

signal degradation per unit length.

•

Data rate: the data rate being sent over the cable. The signal

degradation of HDMI cables increases with data rate.

•

Edge rates: the edge rates of the source input. Slower input

edges result in more significant data eye closure at the end

of a cable.

•

Receiver sensitivity: the sensitivity of the terminating

receiver.

As such, specific cable types and lengths are not recommended

for use with a particular equalizer setting. In nearly all applica-

tions, the AD8196 equalization level can be set to high, or 12 dB,

for all input cable configurations at all data rates, without

degrading the signal integrity.

THE AD8196 AS A SINGLE-CHANNEL BUFFER

The AD8196 can be used as a single-channel TMDS buffer

configuration, the AD8196 connects both the high speed and

low speed channels of Input A to their respective outputs, sets

the input equalization level to 6 dB, the output pre-emphasis

level to 0 dB, enables both the output and input terminations,

and provides a fully functioning HDMI link with TMDS

buffering.

The AD8196 enters this default state whenever the RESET pin

is pulled to low in accordance with the specification in Table 1.

PCB LAYOUT GUIDELINES

The AD8196 is used to switch two distinctly different types of

signals, both of which are required for HDMI and DVI video.

These signal groups require different treatment when laying out

a PC board.

The first group of signals carries the audiovisual (AV) data.

HDMI/DVI video signals are differential, unidirectional, and

high speed (up to 2.25 Gbps). The channels that carry the video

data over the PCB must be controlled impedance, terminated at

the receiver, and capable of operating at the maximum specified

system data rate. It is especially important to note that the

differential traces that carry the TMDS signals should be

designed with a controlled differential impedance of 100 Ω. The

AD8196 provides single-ended 50 Ω terminations on-chip for

both its inputs and outputs, and both the input and output

terminations can be enabled or disabled through the serial

interface. Transmitter termination is not required by the HDMI

1.3 standard but its inclusion improves the overall system signal

integrity.

The audiovisual (AV) data carried on these high speed channels

is encoded by a technique called transition minimized differ-

ential signaling (TMDS) and in the case of HDMI, is also encrypted

according to the high bandwidth digital copy protection (HDCP)

standard.

The second group of signals consists of low speed auxiliary

control signals used for communication between a source and a

sink. Depending upon the application, these signals can include

and HDCP encryption keys between the source and the sink),

the consumer electronics control (CEC) line, and the hot plug

detect (HPD) line. These auxiliary signals are bidirectional, low

speed, and transferred over a single-ended transmission line

that does not need to have controlled impedance. The primary

concern with laying out the auxiliary lines is ensuring that they

capacitive loading.

TMDS Signals

In the HDMI/DVI standard, four differential pairs carry the

TMDS signals. In DVI, three of these pairs are dedicated to

carrying RGB video and sync data. For HDMI, audio data is

interleaved with the video data; the DVI standard does

not incorporate audio information. The fourth high speed

differential pair is used for the AV data-word clock, and runs

at one-tenth the speed of the TMDS data channels.

The four high speed channels of the AD8196 are identical.

No concession was made to lower the bandwidth of the fourth

channel for the pixel clock, so any channel can be used for any

TMDS signal. The user chooses which signal is routed over

which channel. Additionally, the TMDS channels are symmetrical;

therefore, the p and n of a given differential pair are inter-

changeable, provided the inversion is consistent across all inputs

and outputs of the AD8196. However, the routing between

inputs and outputs through the AD8196 is fixed. For example,

Output Channel 0 always switches between Input A0 and

Input B0, and so forth.

The AD8196 buffers the TMDS signals and the input traces can

be considered electrically independent of the output traces. In

most applications, the quality of the signal on the input TMDS

traces are more sensitive to the PCB layout. Regardless of the

data being carried on a specific TMDS channel, or whether the

TMDS line is at the input or the output of the AD8196, all four

high speed signals should be routed on a PCB in accordance

with the same RF layout guidelines.