Nexperia

74LVC161

Presettable synchronous 4-bit binary counter; asynchronous reset

5. Pinning information

5.1. Pinning

74LVC161

MR

VCC

CP

TC

D0

Q0

D1

Q1

D2

Q2

D3

Q3

CEP

CET

GND

PE

001aad086

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Fig. 7. Pin configuration SOT109-1 (SO16) and

SOT403-1 (TSSOP16)

001aad087

74LVC161

CEP

CET

D3

Q3

D2

Q2

D1

Q1

D0

Q0

CP

TC

GND(1)

Transparent top view

7

10

6

11

5

12

4

13

3

14

2

15

terminal 1

index area

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 8. Pin configuration SOT763-1 (DHVQFN16)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

MR

1

synchronous master reset (active LOW)

CP

2

clock input (LOW-to-HIGH, edge-triggered)

D0, D1, D2, D3

3, 4, 5, 6

data input

CEP

7

count enable input

GND

8

ground (0 V)

PE

9

parallel enable input (active LOW)

CET

10

count enable carry input

Q0, Q1, Q2, Q3

14, 13, 12, 11

flip-flop output

TC

15

terminal count output

VCC

16

supply voltage

74LVC161

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 7 — 22 September 2021

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