Nexperia

74LVC161

Presettable synchronous 4-bit binary counter; asynchronous reset

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aaf615

VCC

VI

VO

DUT

CL

RT

RL

PULSE

GENERATOR

Test data is given in Table 9. Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

Fig. 14. Test circuit for measuring switching times

Table 9. Test data

Input

Load

Supply voltage

VI

tr, tf

CL

RL

1.2 V

VCC

≤ 2 ns

30 pF

1 kΩ

1.65 V to 1.95 V

VCC

≤ 2 ns

30 pF

1 kΩ

2.3 V to 2.7 V

VCC

≤ 2 ns

30 pF

500 Ω

2.7 V

2.7 V

≤ 2.5 ns

50 pF

500 Ω

3.0 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF

500 Ω

74LVC161

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 7 — 22 September 2021

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