Nexperia

74LVC161

Presettable synchronous 4-bit binary counter; asynchronous reset

mna912

tPHL

tPLH

VM

VM

TC output

CET input

GND

VI

VOH

VOL

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 10. Input (CET) to output (TC) propagation delays

mna913

MR input

CP input

Qn, TC output

tPHL

tW

trec

VM

VOH

VI

VI

GND

GND

VOL

VM

VM

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 11. Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays, and the master

reset to clock (CP) removal times

mna914

GND

GND

GND

th

th

tsu

tsu

tsu

th

th

tsu

VM

VM

VM

VI

VI

CP input

PE input

Dn input

VI

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 12. Set-up and hold times for the input (Dn) and parallel enable input (PE)

74LVC161

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 7 — 22 September 2021

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