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ADP1822ARQZ-R7 数据表(PDF) 3 Page - Analog Devices

部件名 ADP1822ARQZ-R7
功能描述  PWM, Step-Down DC-to-DC Controller with Margining and Tracking
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP1822ARQZ-R7 数据表(HTML) 3 Page - Analog Devices

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ADP1822
Rev. B | Page 3 of 24
SPECIFICATIONS
VVCC = VPVCC = VSHDN = VFREQ = VTRKN = 5 V, SYNC = MAR = MSEL = GND. All limits at temperature extremes are guaranteed via
correlation using standard statistical quality control (SQC). TA = 25°C, unless otherwise specified.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Input Voltage
3.0
5.5
V
Undervoltage Lockout Threshold
VVCC rising
2.5
2.7
2.9
V
Undervoltage Lockout Hysteresis
VVCC
0.1
V
Quiescent Current
IVCC + IVCC, not switching
1
2
mA
Shutdown Current
SHDN = GND
10
μA
Power Stage Supply Voltage
1.0
24
V
ERROR AMPLIFER
FB Regulation Voltage
TA = −40°C to +85°C
594
600
606
mV
FB Input Bias Current
–100
+1
+100
nA
Error Amplifier Open-Loop Voltage Gain
70
dB
COMP Output Sink Current
600
μA
COMP Output Source Current
110
μA
PWM CONTROLLER
PWM Peak Ramp Voltage
1.25
V
DL Minimum On Time
FREQ = VCC (300 kHz)
140
170
200
ns
SOFT START
SS Pull-Up Resistance
SS = GND
95
kΩ
SS Pull-Down Resistance
VSS = 0.6 V
1.65
2.5
4.2
kΩ
OSCILLATOR
Oscillator Frequency
FREQ = GND, TA = −40°C to +85°C
250
310
375
kHz
FREQ = VCC, TA = −40°C to +85°C
470
570
720
kHz
Synchronization Range
FREQ = GND
300
600
kHz
FREQ = VCC
600
1200
kHz
SYNC Minimum Pulse Width
80
ns
CURRENT SENSE
CSL Threshold Voltage
Relative to PGND
−30
0
+30
mV
CSL Output Current
VCSL = 0 V, TA = −40°C to +85°C
42
50
54
μA
Current Sense Blanking Period
160
ns
GATE DRIVERS
DH Rise Time
CGATE = 3 nF, VDH = VIN, VBST − VSW = 5 V
16
ns
DH Fall Time
CGATE = 3 nF, VDH = VIN, VBST − VSW = 5 V
12
ns
DL Rise Time
CGATE = 3 nF, VDL = VIN
19
ns
DL Fall Time
CGATE = 3 nF, VDL = 0 V
13
ns
DL Low to DH High Dead Time
33
ns
DH Low to DL High Dead Time
42
ns
VOLTAGE MARGINING
High Output Voltage Margin Resistance
MUP to FB, VMAR = VMSEL = 5 V
20
Ω
Low Output Voltage Margin Resistance
MDN to FB, VMAR = 5 V, VMSEL = 0 V
20
Ω
TRACKING
Tracking Comparator Input Offset
–200
+200
mV
Tracking Comparator Delay
100
ns
Tracking Comparator Common-Mode Input Voltage Range
0
VVCC
V
TRKP Pull-Up Resistance
Pull-up to VCC
200
kΩ



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