ADP1822

Rev. B | Page 16 of 24

FEEDBACK VOLTAGE DIVIDER

For example, for an output voltage of 1.0 V and a ±5% margin,

choose

The output regulation voltage is set through the feedback

voltage divider. The output voltage is reduced through the

voltage divider and drives the FB feedback input. The regulation

threshold at FB is 0.6 V. For the low-side resistor of the voltage

divider, R

(16)

Thus,

BOT

, use 10 kΩ. A larger value resistor can be used but

results in a reduction in output voltage accuracy. Choose R

kΩ

67

.

6

=

⎥

⎦

⎤

⎢

⎣

⎡

−

=

FB

FB

OUT

BOT

TOP

V

V

V

R

R

TOP

to

set the output voltage by

(17)

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

=

FB

FB

OUT

BOT

TOP

V

V

V

R

R

(13)

and

(

)(

)

kΩ

80

=

⎥

⎦

⎤

⎢

⎣

⎡

+

=

MUP

BOT

TOP

BOT

TOP

UP

K

R

R

R

R

R

where:

R

(18)

TOP

is the high-side voltage divider resistance.

V

and

OUT

is the regulated output voltage.

V is the feedback regulation threshold, 0.6 V.

kΩ

7

.

46

1

=

⎥

⎦

⎤

⎢

⎣

⎡

−

−

⎥

⎦

⎤

⎢

⎣

⎡

=

MDN

OUT

FB

MDN

TOP

DN

K

V

V

K

R

R

FB

(19)

SETTING THE VOLTAGE MARGIN

The output voltage is margined by connecting a resistor from

FB to GND (for the high margin voltage) or FB to the output

voltage (for low margin voltage). The switches for margining are

supplied inside the ADP1822 and are controlled by the MAR

and MSEL inputs (see

COMPENSATING THE REGULATOR

The output of the error amplifier at COMP is used to compensate

the regulation control system. Connect a resistor capacitor (RC)

network from COMP to FB to compensate the regulator.

Table 1).

The first step of selecting the compensation components is

determining the desired regulation-control crossover frequency,

f

Choose the high margin resistor by

()(

)

MUP

BOT

TOP

BOT

TOP

UP

K

R

R

R

R

R

⎥

⎦

⎤

⎢

⎣

⎡

+

=

CO

(14)

. Choose a crossover frequency approximately 1/10 of the

switching frequency, or

10

SW

CO

f

f

=

(20)

where:

R

The characteristics of the output capacitor affect the compensation

required to stabilize the regulator. The output capacitor acts

with its ESR to form a zero. Calculate the ESR zero frequency by

BOT

is the bottom voltage divider resistor from FB to GND.

voltage.

Choose the low margin resistor by the equation

⎥

⎦

⎤

⎢

⎣

⎡

−

−

⎥

⎦

⎤

⎢

⎣

⎡

=

MDN

OUT

FB

MDN

TOP

DN

K

V

V

K

R

R

1

(15)

where:

voltage.

ESR

C

f

OUT

ESRZ

π

2

1

=

(21)

Note that as similar capacitors are placed in parallel, the ESR

zero frequency remains the same.

≤ f

CO

/2, use the ESR zero to stabilize the regulator (see the

section). If f

≥ 2f

Compensation Using the ESR Zero

ESRZ

CO

, use a

feed-forward network to stabilize the regulator (see the

then use both the ESR zero and feed-forward zeros to stabilize

the regulator (see the Compensation Using Both the ESR and

Feed-Forward Zeros section).