ADP1822

Rev. B | Page 13 of 24

If the output voltage is precharged prior to turn-on, the

ADP1822 prevents reverse inductor current that would discharge

the output voltage. Once the voltage at SS exceeds the 0.6 V

regulation voltage, the reverse current is re-enabled to allow the

output voltage regulation to be independent of load current.

To override the soft start feature, leave SS unconnected. This

allows the output voltage to rise as quickly as possible and

eliminates the soft start period.

HIGH-SIDE DRIVER (BST AND DH)

Gate drive for the high-side power MOSFET is generated by a

flying capacitor boost circuit. This circuit allows the high-side

N-channel MOSFET gate to be driven above the input voltage,

allowing full enhancement of and a low voltage drop across the

MOSFET. The circuit is powered from a flying capacitor from

SW to BST that in turn is powered from the PVCC gate driver

voltage. When the low-side switch is turned on, SW is driven to

PGND, and the flying capacitor is charged from PVCC through

an external Schottky rectifier. The capacitor stores sufficient

charge to power BST to drive DH high and to fully enhance the

high-side N-channel MOSFET. Use a flying capacitor value

greater than 100× the high-side MOSFET input capacitance.

LOW-SIDE DRIVER (DL)

DL is the gate drive for the low-side power MOSFET synchronous

rectifier. Synchronous rectification reduces conduction losses

developed by a conventional rectifier by replacing it with a

low resistance MOSFET switch. DL turns on the synchronous

rectifier by driving the gate voltage to PVCC. The MOSFET is

turned off by driving the gate voltage to PGND.

An active dead time reduction circuit reduces the break-before-

make time of the switching to limit the losses due to current

flowing through the synchronous rectifier body diode or

external Schottky rectifier.

INPUT VOLTAGE RANGE

The ADP1822 takes its internal power from the VCC and

PVCC inputs. PVCC powers the low-side MOSFET gate drive

(DL), and VCC powers the internal control circuitry. Both of

these inputs are limited to between 3.0 V and 5.5 V. Bypass

PVCC to PGND with a 1 μF or greater capacitor. Bypass VCC

to GND with a 0.1 μF or greater capacitor.

The power input to the dc-to-dc converter can range between

1.2× the output voltage up to 24 V. Bypass the power input to

PGND with a suitably large capacitor. See the Selecting the

Input Capacitor section.

SETTING THE OUTPUT VOLTAGE

The output voltage is set using a resistive voltage divider from

the output to FB. The voltage divider drops the output voltage

to the 0.6 V FB regulation voltage to set the regulation output

voltage. The output voltage is set to voltages as low as 0.6 V and

as high as 85% of the minimum power input voltage (see the

Feedback Voltage Divider section).

SWITCHING FREQUENCY CONTROL

The ADP1822 has a logic-controlled frequency select input,

FREQ, that sets the switching frequency to 300 kHz or 600 kHz.

Drive FREQ low for 300 kHz and drive it high for 600 kHz.

The SYNC input is used to synchronize the converter switching

frequency to an external signal. The synchronization range is

300 kHz to 1.2 MHz. The acceptable synchronization frequency

range is limited to twice the nominal switching frequency set by

FREQ. For lower frequency synchronization, between 300 kHz

and 600 kHz, connect FREQ to GND. For higher frequency

synchronization, between 480 kHz and 1.2 MHz, connect FREQ

to VCC (see the Synchronizing the Converter section for more

information).

COMPENSATION

The control loop is compensated by an external series RC

network from COMP to FB and sometimes requires a series RC

in parallel with the top voltage divider resistor. COMP is the

output of the internal error amplifier.

The internal error amplifier compares the voltage at FB to the

internal 0.6 V reference voltage. The difference between the two

(the feedback voltage error) is amplified by the error amplifier. To

optimize the ADP1822 for stability and transient response for a

given set of external components and input/output voltage

conditions, choose the compensation components. For more

information on choosing the compensation components, see the

Compensating the Regulator section.

POWER-GOOD INDICATOR

The ADP1822 features an open-drain power-good output,

PWGD, that sinks current when the output voltage drops

8.3% below or 25% above the nominal regulation voltage. Two

comparators measure the voltage at FB to set these thresholds.

The PWGD output also sinks current if overtemperature or

input undervoltage conditions are detected. It is operational

Use this output as a simple power-good signal by connecting a

pull-up resistor from PWGD to an appropriate supply voltage.

SHUTDOWN CONTROL

The ADP1822 dc-to-dc converter features a low power shut-

down mode that reduces quiescent supply current to 1 μA. To

shut down the ADP1822, drive SHDN low. To turn it on, drive

SHDN high. For automatic startup, connect SHDN to VCC.