ADT7408

Rev. 0 | Page 11 of 24

CONFIGURATION REGISTER (READ/WRITE)

This 16-bit read/write register stores various configuration modes for the ADT7408, as shown in Table 8 and the following bit map.

Note that RFU means reserved for future use.

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RFU

RFU

RFU

RFU

RFU

Hysteresis

Shut-

down

mode

Critical

lock bit

Alarm

lock bit

Clear

event

Event

output

status

Event

output

control

Critical

event

only

Event

polarity

Event

mode

Table 8. Configuration Mode Description

Bit

Description

D0

Event mode

0: Comparator output mode (default)

1: Interrupt mode

When either lock bit (D6 and D7) is set, this bit cannot be altered until unlocked.

D1

Event polarity

0: Active low (default)

1: Active high

When either lock bit (D6 and D7) is set, this bit cannot be altered until unlocked.

D2

Critical event only

0: Event output on alarm or critical temperature event (default)

1: Event only if temperature is above the value in the critical temperature trip register

When either lock bit (D6 and D7) is set, this bit cannot be altered until unlocked.

D3

Event output control

0: Event output disabled (default)

1: Event output enabled

When either lock bit (D6 and D7) is set, this bit cannot be altered until unlocked.

D4

Event output status (read only)

0: Event output condition is not being asserted by this device

1: Event output pin is being asserted by this device due to alarm window or critical trip condition

The actual cause of an event can be determined from the read of the temperature value register. Interrupt events can be cleared

by writing to the clear event bit. Writing to this bit has no effect on the output status because it is a read function only.

D5

Clear event (write only)

0: No effect

1: Clears an active event in interrupt mode

Writing to this register has no effect in comparator mode. When read, this bit always returns 0. Once the DUT temperature

is greater than the critical temperature, an event cannot be cleared (see Figure 12).

D6

Alarm window lock bit

0: Alarm trips are not locked and can be altered (default)

1: Alarm trip register settings cannot be altered

This bit is initially cleared. When set, this bit returns a 1 and remains locked until cleared by internal power on reset. These bits

can be written with a single write and do not require double writes.

D7

Critical trip lock bit

0: Critical trip is not locked and can be altered (default)

1: Critical trip register settings cannot be altered

This bit is initially cleared. When set, this bit returns a 1 and remains locked until cleared by internal power on reset. These bits

can be written with a single write and do not require double writes.

D8

Shutdown mode

0: TS enabled (default)

1: TS shut down

When shut down, the thermal sensing device and ADC are disabled to save power. No events are generated. When either lock bit

is set, this bit cannot be set until unlocked. However, it can be cleared at any time.