ADT7408

Rev. 0 | Page 17 of 24

SERIAL INTERFACE

compatible serial interface. The ADT7408 is connected to this

bus as a slave and is under the control of a master device.

EVENT#

ADT7408

PULLUP

PULLUP

10kΩ

10kΩ

10kΩ

A0

SDA

SCL

GND

A1

A2

Serial Bus Address

serial address. The four MSBs of this address for the ADT7408 are

set to 0011. The three LSBs are set by Pin 1, Pin 2, and Pin 3

(A0, A1, and A2). These pins can be configured either low or

high, permanently or dynamically, to give eight different

address options. Table 11 shows the different bus address

options available. Recommended pull-up resistor value on the

SDA and SCL lines is 2.2 kΩ to 10 kΩ .

BINARY

A6 to A0

HEX

0011 0 0 0

0x18

0011 0 0 1

0x19

0011 0 1 0

0x1A

0011 0 1 1

0x1B

0011 1 0 0

0x1C

0011 1 0 1

0x1D

0011 1 1 0

0x1E

0011 1 1 1

0x1F

activity on the SDA line. After this timeout the ADT7408 resets

the SDA line back to its idle state (SDA set to high impedance)

and waits for the next start condition.

The serial bus protocol operates as follows:

1.

The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial

data line SDA, while the serial clock line, SCL, remains

high. This indicates that an address/data stream follows.

All slave peripherals connected to the serial bus respond to

the start condition and shift in the next eight bits,

consisting of a 7-bit address (MSB first) plus a R/W bit.

The R/W bit determines whether data is written to, or read

from, the slave device.

2.

The peripheral with the address corresponding to the

transmitted address responds by pulling the data line low

during the low period before the ninth clock pulse, known

as the acknowledge bit. All other devices on the bus now

remain idle while the selected device waits for data to be

read from or written to it. If the R/W bit is a 0, then the

master writes to the slave device. If the R/W bit is a 1, the

master reads from the slave device.

3.

Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit

from the receiver of data. Transitions on the data line must

occur during the low period of the clock signal and remain

stable during the high period, because a low to high

transition when the clock is high can be interpreted as a

stop signal.

4.

When all data bytes have been read or written, stop

conditions are established. In write mode, the master pulls

the data line high during the 10th clock pulse to assert a

stop condition. In read mode, the master device pulls the

data line high during the low period before the ninth clock

pulse. This is known as no acknowledge. The master then

takes the data line low during the low period before the

10th clock pulse, then high during the 10th clock pulse to

assert a stop condition.

Any number of bytes of data can be transferred over the serial

bus in one operation. However, it is not possible to mix read

and write in one operation because the type of operation is

determined at the beginning and cannot subsequently be

changed without starting a new operation.

by the device until after this address has been sent twice. On the

eighth SCL cycle of the second valid communication, the serial

bus address is latched in. This is the SCL cycle directly after the