AD5522

Preliminary Technical Data

Rev. PrL | Page 32 of 45

WRITE DAC REGISTER

The DAC input, gain and offset registers are addressed through a combination of PMU bits (Bits 27 through 24) and MODE bits (Bits 23

and 22). Bits A5 through A0 address each of the DAC levels on chip. D15 through D0 are the DAC data Bits when writing to these

registers. PMU address bits allow addressing to DAC across any combination of PMU channels.

Table 19. DAC Register Bits

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

B15 to B0

RD/WR

PMU3

PMU2

PMU1

PMU0

MODE1

MODE0

A5

A4

A3

A2

A1

A0

DATA BITS D15 (MSB to D0 (LSB)

Table 20. DAC Register Functions

Bit

Bit name

Description

28 (MSB)

RD/WR

When low, a write function takes place to the selected register, while if the RD/WR bit is set high, this initiates a

readback sequence of PMU, Alarm, Comparator, System Control or DAC register as determined by address bits.

27

PMU3

26

PMU2

25

PMU1

24

PMU0

Bits PMU3 through PMU0 address each of the PMU and DAC channels in the device. This allows individual

control of each DAC channel or any manner of combined addressing in addition to multi-channel programming.

B27

B26

B25

B24

B23

B22

SELECTED REGISTER

PMU3

PMU2

PMU1

PMU0

MODE1

MODE0

CH3

CH2

CH1

CH0

0

0

0

0

0

0

Write to System Control Register

0

0

0

1

×

×

×

CHO

0

0

1

0

×

×

CH1

×

0

0

1

1

×

×

CH1

CH0

0

1

0

0

×

CH2

×

×

-

-

-

-

-

-

-

-

1

0

0

0

CH3

×

×

×

-

-

-

-

-

-

-

-

1

1

1

0

CH3

CH2

CH1

×

1

1

1

1

Select DAC or PMU Registers.

See below

CH3

CH2

CH1

CH0

23

MODE1

22

MODE0

Mode Bits, MODE0 and MODE1 allow addressing of the DAC gain (m), offset (c ) or input register (x1)

MODE1

MODE0

Action

0

0

System Control Register or PMU Register

0

1

DAC Gain (m) Register

1

0

DAC Offset (c) Register

1

1

DAC Input Data Register, (x1)

DAC REGISTER SPECIFIC BITS

21,20,19

A5,A4,A3

DAC Address Bits. A5 to A3 select which register set is addressed. See Table 21

18,17,16

A2,A1,A0

DAC Address Bits, A2 to A0 select which DAC is addressed. See Table 21

15 to 0(LSB)

D15 (MSB) to D0(LSB)

16 DAC Data bits. D15 MSB.