AD5665-RBRUZ-2 datasheet(21/32 Pages) AD

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Preliminary Technical Data

AD5625R/AD5645R/AD5665R, AD5625/AD5665

Rev. PrA. | Page 21 of 32

The AD5625R/AD5645R/AD5665R, AD5625/AD5665 support

standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz)

data transfer modes. High-speed operation is only available on

selected models. See the Ordering Information on the back

page for a full list of models. Support is not provided for 10-bit

addressing and general call addressing.

The AD5625R/AD5645R/AD5665R, AD5625/AD5665 each

have a 7-bit slave address. 10-pin versions of the part have a

slave address whose five MSBs are 00011, and the two LSBs are

set by the state of the ADDR address pin, which determines the

state of the A0 and A1 address bits. 14-pin versions of the part

have a slave address whose three MSBs are 001, and the four

LSBs are set by the ADDR1 and ADDR2 address pins, which

determine the state of the A0 and A1, A2 and A3 address bits

respectively.

The ADDR pin is three-state, and can be set as shown in Table

8 to give three different addresses.

Table 8. ADDR Pin Settings (10-pin package)

ADDR PIN CONNECTION

VDD

No Connection

GND

The ADDR1 and ADDR2 pins are also three-state, and can be

set as shown in Table 9 to give a total of 9 different addresses.

Table 9. ADDR1, ADDR2 Pin Setting (14-pin Package)

ADDR2

ADDR1

VDD

GND

VDD

GND

VDD

GND

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high. The following byte is the

address byte, which consists of the 7-bit slave address. The

slave address corresponding to the transmitted address

responds by pulling SDA low during the ninth clock pulse

(this is termed the acknowledge bit). At this stage, all other

devices on the bus remain idle while the selected device

waits for data to be written to, or read from, its shift

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge

bit). The transitions on the SDA line must occur during the

low period of SCL and remain stable during the high period

of SCL.

3. When all data bits have been read or written, a stop

condition is established. In write mode, the master pulls the

SDA line high during the 10th clock pulse to establish a

stop condition. In read mode, the master issues a no

acknowledge for the ninth clock pulse (that is, the SDA line

remains high). The master then brings the SDA line low

before the 10th clock pulse, and then high during the 10th

clock pulse to establish a stop condition.

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