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AD5665-RBRUZ-2 数据表(PDF) 22 Page - Analog Devices

部件名 AD5665-RBRUZ-2
功能描述  Quad, 12-/14-/16-Bit nanoDACs with 5ppm/째C On-chip Ref, I2C Interface
PDF  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5665-RBRUZ-2 数据表(HTML) 22 Page - Analog Devices

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AD5625R/AD5645R/AD5665R, AD5625/AD5665
Preliminary Technical Data
Rev. PrA. | Page 22 of 32
R/W
0
SCL
SDA
0
0
1
1
A1
A0
DB23 D B22 DB2 1 D B20 DB19 DB 18 D B17 DB1 6
ACK. BY
AD56x5
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
19
1
ACK. BY
AD56x5
9
DB7
DB6
DB5
D B4
D B3
D B2
DB 1
DB0
ACK. BY
AD56x5
STOP BY
MASTER
19
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14 DB 13 D B12 DB 11 D B10 DB 9
DB8
ACK. BY
AD56x5
1
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 52. I2C Write Operation (10-Pin Package)
R/W
0
SCL
SDA
01
A1
A0
DB23 DB 22 DB 21 DB2 0 DB19 DB1 8 DB1 7 D B16
ACK. BY
AD56x5
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
19
1
ACK. BY
AD56x5
9
DB7
DB6
DB5
DB4
D B3
DB2
DB 1
DB0
ACK. BY
AD56x5
STOP BY
MASTER
19
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB 14 DB1 3 DB1 2 DB 11 DB10 DB9
DB 8
ACK. BY
AD56x5
1
A3
A2
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 53. I2C Write Operation (14-Pin Package)
WRITE OPERATION
When writing to the AD5625R/AD5645R/AD5665R,
AD5625/AD5665, the user must begin with a start command
followed by an address byte (R/W = 0), after which the DAC
acknowledges that it is prepared to receive data by pulling SDA
low. The AD5665 requires two bytes of data for the DAC and a
command byte that controls various DAC functions. Three
bytes of data must therefore written to the DAC, the command
byte followed by the most significant data byte and the least
significant data byte, as shown in Figures 52 and 53. All these
data bytes are acknowledged by the
AD5625R/AD5645R/AD5665R, AD5625/AD5665. A stop
condition follows.
READ OPERATION
When reading data back from the
AD5625R/AD5645R/AD5665R, AD5625/AD5665, the user
begins with a start command followed by an address byte (R/W
= 1), after which the DAC acknowledges that it is prepared to
transmit data by pulling SDA low. Two bytes of data are then
read from the DAC, which are both acknowledged by the
master as shown in Figures 54 and 55. A stop condition follows.
Note that the only data that can be read back from the AD56x5
is the contents of the input shift register (see section on Control
Register).



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