AD5665-RBRUZ-2 datasheet(27/32 Pages) AD

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Preliminary Technical Data

AD5625R/AD5645R/AD5665R, AD5625/AD5665

Rev. PrA. | Page 27 of 32

Power-down modes

1 kΩ pulldown to GND

100 kΩ pulldown to GND

Three-state, high impedance

RESISTOR

NETWORK

VOUT

RESISTOR

STRING DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 64. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string, and

other associated linear circuitry are shutdown when power-

down mode is activated. However, the contents of the DAC

power-down is typically 4 µs for VDD = 5 V and for VDD = 3 V.

Figure 63 shows the format of the power up/down command.

Note that, during the power up/down command, the DAC

address bits A2 – A0 are ignored.

POWER-ON-RESET AND SOFTWARE RESET

The AD56x5 contains a power-on reset circuit that controls the

output voltage during power-up. The 10-pin version of the

device powers up to 0V. The 14-pin version has a Power On

Reset (POR) pin that allows the output voltage to be selected. By

connecting the POR pin low, the AD56x5 output powers up to 0

V; by connecting the POR pin high, the AD56x5 output powers

up to midscale. The output remains powered up at this level

until a valid write sequence is made to the DAC. This is useful

in applications where it is important to know the state of the

output of the DAC while it is in the process of powering up.

Any events on LDAC or CLR during power-on reset are

ignored.

There is also a software reset function. Command 101 is the

software reset command. The software reset command contains

two reset modes that are software programmable by setting bit

DB0 in the input shift register.

Table 13 shows how the state of the bit corresponds to the

software reset modes of operation of the devices. Figure 64

shows the contents of the input shift register during the

software reset mode of operation.

Table 13. Software Reset Modes for the

AD5625R/AD5645R/AD5665R, AD5625/AD5665

DB0

Registers reset to zero

DAC register

Input shift register

1 (Power-On Reset)

DAC register

Input shift register

LDAC register

Power-down register

Internal reference setup register

CLEAR PIN (CLR)

The 14-pin version of the AD56x5 has an asynchronous clear

input. The CLR input is falling edge sensitive. While CLR is

low, all LDAC pulses are ignored. When CLR is activated, zero

scale is loaded to all input and DAC registers. This clears the

output to 0 V. The part exits clear code mode on the 24th

falling edge of the next write to the part. If CLR is activated

during a write sequence, the write is aborted. If CLR is

activated during high speed mode the part will exit high speed

mode to fast mode.

Figure 65. Reset Command

INTERNAL REFERENCE SETUP (-R VERSIONS)

The on-chip reference is off at power-up by default. It can be

turned on by sending the reference setup command (111) and

setting DB0 in the input shift register. Table 14 shows how the

state of the bit corresponds to the mode of operation.

Table 14. Reference Setup Command

(DB0)

Action

Internal reference off (default)

Internal reference on

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