AD6624SSLASHPCB datasheet(29/40 Pages) AD

29 / 40 page

REV. B

AD6624

–29–

Regardless of whether the chip is a Serial Bus Master or is in

Serial Slave mode, the AD6624 Serial Port functions are identi-

cal except for the source of the SCLK and SDFS pins.

SCLK

SCLK is an output when SBM (SBM0 or register bit for Serial

Ports 1, 2, and 3) is high; SCLK is an input when SBM (SBM0

or register bit for Serial Ports 1, 2, and 3) is low in serial slave

mode. In either case, the SDIN input is sampled on the falling

edge of SCLK and all outputs are switched on the rising edge of

SCLK. The SDFS pin is sampled on the falling edge of SCLK.

This allows the AD6624 to recognize the SDFS in time to initiate a

frame on the very next SCLK rising edge. The maximum speed

of this port is 80 MHz.

SDIN

SDIN is the Serial Data Input. Serial Data is sampled on the

falling edge of SCLK. This pin is used in the serial control

mode to write the internal control registers of the AD6624.

These activities are described later in the Serial Port Control

section. The Serial Input Port is self-framing and bears no fixed

relationship to either SDFS or SDFE.

SDO

SDO is the Serial Data Output. Serial output data is shifted on

the rising edge of SCLK. On the very next SCLK rising edge

after an SDFS, the MSB of the I data from the channel is shifted.

On every subsequent SCLK edge, a new piece of data is shifted

out on the SDO pin until the last bit of data is shifted out. The

last bit of data shifted is the LSB of the Channel’s Q data. SDO

is three-stated when the serial port is outside its time-slot. This

allows the AD6624 to share the SDIN of a DSP with other

AD6624s or other devices.

SDFS

SDFS is the Serial Data Frame Sync signal. SDFS is an output

when SBM (SBM0 or register bit for Serial Ports 1, 2, and 3)

is high in the Master mode. SDFS is an input when SBM

(SBM0 or register bit for Serial Ports 1, 2, and 3) is low in the

Slave mode. SDFS is sampled on the falling edge of SCLK.

When SBM is sampled low, the AD6624 serial port will func-

tion as a serial slave. In this mode, the port is silent until the

DSP issues a frame sync. When the AD6624 detects an SDFS

on the falling edge of a DSP-generated serial clock, on the next

rising edge of the serial clock, the AD6624 enables the output

driver and shifts the MSB of the I word. Data is shifted until the

LSB of the Q word has been sent. On the LSB of the Q word,

the AD6624 generates an SDFE, which can be cascaded to the

next SDFS on a TDM serial chain or to the DSP to indicate

that the last bit has been sent.

When SBM is sampled high, the chip functions as a serial bus

master. In this mode, the AD6624 is responsible for generating

serial control data. Three modes of that operation are set via

channel address 0xA9 Bits 8–7. Each behaves a little differently,

as detailed below.

In the first mode (0xA9 Bits 8–7:00), the SDFS is valid for one

complete clock cycle prior to the data shift. On the next clock

cycle, the AD6624 begins shifting serial data. In the second mode,

(0xA9 Bits 8–7:01), the SDFS is high for the entire time that

valid bits are being shifted. The SDFS bit goes high concurrent

with the first bit shifted out of the AD6624 and returns low

after the last bit is shifted out of the AD6624. In the third mode

(0xA9 Bits 8–7:10), the SDFS bit goes high as in the first mode,

one clock cycle prior to the actual data. However, a second

SDFS is inserted one clock cycle prior to the shift of the first

Q bit. In this manner, each word out of the AD6624 is accom-

panied by an SDFS.

SDFE

SDFE is the Serial Data Frame End output. SDFE will go high

during the last SCLK cycle (LSB of the Q word) of an active

time-slot. The SDFE output of a master AD6624 channel can

be tied to the input SDFS of an AD6624 channel in Serial Slave

mode in order to provide a hard-wired time-slot scenario. When

the last bit of SDO data is shifted out of the Master AD6624, the

SDFE signal will be driven high by the same SCLK rising edge

on which this bit is clocked out. On the falling edge of this

SCLK cycle, the slaved serial port will sample its SDFS signal,

which is hard-wired to the SDFE of the master. On the very

next SCLK rising edge, data of the slave will start shifting. There

will be no rest between the time slots of the master and slave.

Serial Word Length

Bits 6–5 of register 0xA9 determine the length of the serial word

(I or Q). If these bits are set to ‘00,’ each word is 12 bits (12

bits for I and 12 more bits for Q). If set to ‘01,’ the serial words

are 16 bits wide, and if set to ‘1x’ (x is don’t care), the word

length is 24 bits.

SDFS Mode

Bits 8–7 of register 0xA9 determine how the SFDS behaves in

Serial Bus Master mode. In Serial Slave mode, the frame sync

must be formatted by programming Bits 8–7 to ‘00.’

The first mode is set by programming Bits 8–7 to ‘00’. In this

mode, the SDFS is valid for one complete clock cycle prior to

the data shift. On the next clock cycle, the AD6624 begins shift-

ing out the digitally processed data stream. Depending on the

bit precision of the serial configuration, either 12, 16, or 24 bits

of I data are shifted out, followed by 12, 16, or 24 bits of Q data.

The second mode is set by programming Bits 8–7 to ‘01.’ In this

mode, the SDFS is high for the entire time that valid bits are

being shifted. The SDFS bit goes high concurrent with the

first bit shifted out of the AD6624 and goes low after the last bit

has been shifted.

The third mode is set by programming Bits 8–7 to ‘1x’ (x is

don’t care). In this mode, the SDFS bit goes high as in the first

mode, one clock cycle prior to the actual data. However, a sec-

ond SDFS is inserted one clock cycle prior to the shift of the first

Q bit. In this manner, each word out of the AD6624 is accompa-

nied by an SDFS.

Mapping RCF Data to the BIST Registers

If Bit 9 of 0xA9 is set, RCF data is routed to the BIST registers.

This allows the filter results to be read from the microprocessor

port. This can be useful when the data must be accessed via a

parallel port and the decimation rate is sufficiently high that

throughput does not become an issue.

0x00–0x7F: Coefficient Memory (CMEM)

This is the Coefficient Memory (CMEM) used by the RCF. It is

memory mapped as 128 words by 20 bits. A second 128 words of

RAM may be accessed via this same location by writing Bit 8 of

the RCF control register high at channel address 0xA4. The

filter calculated will always use the same coefficients for I and

Q. By using memory from both of these 128 blocks, a filter up

to 160 taps can be calculated. Multiple filters can be loaded

and selected with a single internal access to the Coefficient

Offset Register at channel address 0xA3.

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