AD6624SSLASHPCB datasheet(24/40 Pages) AD

24 / 40 page

REV. B

AD6624

–24–

1. Note that the time from when RDY (Pin 57) goes high to

when the NCO begins processing data is the contents of the NCO

Freq Hold-Off counter (0x84) plus seven master clock cycles.

2. Write the NCO Freq Hold-Off (0x84) counter to the appro-

priate value (greater than 1 and less then 2

16–1).

3. Write the NCO Frequency register(s) to the new desired

frequency.

4. Write the Hop bit and the Sync(s) bit high (Ext Address 4).

5. This starts the NCO Freq Hold-Off counter counting down.

The counter is clocked with the AD6624 CLK signal. When

it reaches a count of one, the new frequency is loaded into

the NCO.

Hop with Pin Sync

The AD6624 includes four Sync pins to provide the most accu-

rate synchronization, especially between multiple AD6624s.

Synchronization of hopping to a new NCO frequency with an

external signal is accomplished using the following method:

1. Note that the time from when the Sync pin goes high to when

the NCO begins processing data is the contents of the NCO Freq

Hold-Off counter (0x84) plus five master clock cycles.

2. Write the NCO Freq Hold-Off counter(s) (0x84) to the

appropriate value (greater than 1 and less than 2

16–1).

3. Write the NCO Frequency register(s) to the new desired

frequency.

4. Set the Hop on Pin Sync bit and the appropriate Sync Pin

Enable high.

5. When the selected Sync pin is sampled high by the AD6624

CLK, it enables the count-down of the NCO Freq Hold-Off

counter. The counter is clocked with the AD6624 CLK signal.

When it reaches a count of one, the new frequency is loaded

into the NCO.

SERIAL OUTPUT DATA PORT

The AD6624 has four configurable serial output ports (SDO0,

SDO1, SDO2, and SDO3). Each port can be operated inde-

pendently of the other, making it possible to connect each to

a different DSP. In the case where a single DSP is required, the

ports can easily be configured to work with a single serial port

on a single DSP. As such, each output may be configured as

either serial master or slave. Additionally, each channel can be

configured independently of the others.

Serial Output Data Format

The AD6624 works with a variety of output data formats. These

include word lengths of 12-, 16-, and 24-bit precision. In addi-

tion to the normal linear binary data format, the AD6624 offers

a floating-point data format to simplify numeric processing.

These formats are 8-bit mantissa with 4-bit exponent, and

12-bit mantissa and 4-bit exponent. These modes are available

regardless of the bit precision of the serial data frame. In the

normal linear binary data format, a programmable internal 4-bit

scaling factor is used to scale the output. See the RCF Output

Scale Factor section and Control Register above for more details.

In all modes, the data is shifted out of the device in Big Endian

format (MSB first).

In floating-point mode, the chip normally determines the expo-

nent automatically; however, the chip can be forced to use the

same exponent for both the real and imaginary portion of the

data. The choice of exponents favors prevention of numerical

overflow at the expense of small number accuracy. However,

this should not be a problem as small numbers imply numbers

close to zero.

Finally, the AD6624 channel can be forced to use a preselected

scale factor if desired. This allows for a consistent range of data

useful to many applications.

Serial Data Frame (Serial Bus Master)

The serial data frame is initiated with the Serial Data Frame Sync

(SDFS0, SDFS1, SDFS2, or SDFS3). As each channel within

the AD6624 completes a filter cycle, data is transferred into the

serial data buffer. In the Serial Bus Master (SBM) mode, the inter-

nal serial controller initiates the SDFS on the next rising edge of

the serial clock. In the AD6624, there are three different modes

in which the frame sync may be generated as a Serial Bus Master.

In the first mode, the SDFS is valid for one complete clock cycle

prior to the data shift. On the next clock cycle, the AD6624 begins

shifting out the digitally processed data stream. Depending on

the bit precision of the serial configuration, either 12, 16, or 24

bits of I data are shifted out, followed by 12, 16, or 24 bits of

Q data. The format of this data will be in one of the formats

listed above. In the second mode, the SDFS is high for the

entire time that valid bits are being shifted. The SDFS bit goes

high concurrent with the first bit shifted out of the AD6624.

I[23:12]

I[1:8]

Q[23:20]

I[7:0]

Q[23:2]

Q[19:8]

Q[23:2]

Q[11:8]

Z, NEW-I

Q[7:0]

Z, NEW-I

SCLK

SDFS

SDFE

SDO

12345678 9 10 12345 67 8 9 20 12 3 4 5 678 9 30 12345678 9 40 12 3 4 5 6 78 9

Figure 29. SDFS Valid for One SCLK Cycle

I[23:12]

I[23:13]

I[23:12]

I[1:8]

Q[23:20]

I[7:0]

Q[23:2]

Q[19:8]

Q[23:2]

Q[11:8]

Z, NEW-I

Q[7:0]

Z, NEW-I

SCLK

SDFS

SDFE

SDO

12345678 9 10 12345 67 8 9 20 12 3 4 5 6 7 8 9 30 12345678 9 40 12 3 4 567 8 9

Figure 30. SDFS Is High During Data Shift

In the final mode, the SDFS bit goes high as in the first mode,

one clock cycle prior to the actual data. However, a second SDFS

is inserted one clock cycle prior to the shift of the first Q bit. In

this manner, each word out of the AD6624 is accompanied by

an SDFS.

SCLK

12345678 9 10 12345 67 8 9 20 12 3 4 5 678 9 30 12345678 9 40 12 3 4 567 8 9

SDFS

SDFE

SDO

I[23:12]

I[23:13]

I[23:12]

I[1:8]

Q[23:20]

I[7:0]

Q[23:2]

Q[19:8]

Q[23:2]

Q[11:8]

Z, NEW-I

Q[7:0]

Z, NEW-I

Figure 31. A Second SDFS Inserted Prior to First Q Bit

Regardless of the mode above, the SDFE behaves the same in

each. On the last bit of the serial frame (least significant bit of

the Q word), the Serial Data Frame End (SDFE) is raised. The

SDFE signal can either be used by the DSP to indicate the end

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