AD6624SSLASHPCB datasheet(35/40 Pages) AD

35 / 40 page

REV. B

AD6624

–35–

Bit 4 causes the normal RSP data on serial channel 0 to be

replaced with read access data. This allows reading the internal

registers over the serial bus. It should be noted that in the mode,

any RSP data will be superceded by internal access data.

Bit 5 allows access to the Input Control Port Registers at channel

addresses 00-07. When this bit is set low, the normal memory

map is accessed. However, when this bit is set, it allows access

to the Input Port Control Registers. Access to these registers

allows the lower and upper thresholds to be set along with dwell

time and other features. When this bit is set, the value in exter-

nal address 6 (CAR) points to the memory map for the Input

Port Control Registers instead of the normal memory map. See

Input Port Control Registers below.

Bits 6–7 are reserved and should be set low.

Data Address Registers

External Address [2-0] form the data registers DR2, DR1, and

DR0 respectively. All internal data words have widths that are less

than or equal to 20 bits. Accesses to External Address [0] DR0

trigger an internal access to the AD6624 based on the address

indicated in the ACR and CAR. Thus during writes to the inter-

nal registers, External Address [0] DR0 must be written last. At

this point, data is transferred to the internal memory indi-

cated in A[9:0]. Reads are performed in the opposite direction.

Once the address is set, External Address [0] DR0 must be the

first data register read to initiate an internal access. DR2 is only

four bits wide. Data written to the upper four bits of this register

will be ignored. Likewise reading from this register will produce

only four LSBs.

Write Sequencing

Writing to an internal location is achieved by first writing the

upper two bits of the address to Bits 1 through 0 of the ACR.

Bits 7:2 may be set to select the channel as indicated above. The

CAR is then written with the lower eight bits of the internal

address (it does not matter if the CAR is written before the

ACR as long as both are written before the internal access).

Data Register 2, (DR2) and Data Register 1 (DR1) must be

written first because the write to Data Register DR0 triggers the

internal access. Data Register DR0 must always be the last

Read Sequencing

Reading from the microport is accomplished in the same manner.

The internal address is set up the same way as the write. A read

from Data Register DR0 activates the internal read, thus register

DR0 must always be read first to initiate an internal read fol-

lowed by DR1 and DR2. This provides the eight LSBs of the

internal read through the microport (D[7:0]). Additional data

registers can be read to read the balance of the internal memory.

Read/Write Chaining

The microport of the AD6624 allows for multiple accesses

while

CS is held low (CS can be tied permanently low if the

microport is not shared with additional devices). The user can

access multiple locations by pulsing the

WR or RD line and

changing the contents of the external 3-bit address bus. Exter-

nal access to the external registers of Table II is accomplished in

one of two modes using the

CS, RD, WR, and MODE inputs.

The access modes are Intel Nonmultiplexed Mode and Motorola

Nonmultiplexed Mode. These modes are controlled by the

MODE input (MODE = 0 for INM, MODE = 1 for MNM).

CS, RD, and WR control the access type for each mode.

Intel Nonmultiplexed Mode (INM)

MODE must be tied low to operate the AD6624 microprocessor

in INM mode. The access type is controlled by the user with

the

CS, RD (DS), and WR (RW) inputs. The RDY (DTACK)

signal is produced by the microport to communicate to the user

that an access has been completed. RDY (

DTACK) goes low at

the start of the access and is released when the internal cycle is

complete. See the timing diagrams for both the read and write

modes in the Specifications.

Motorola Nonmultiplexed Mode (MNM)

MODE must be tied high to operate the AD6624 microprocessor

in MNM mode. The access type is controlled by the user with

the

CS, DS (RD), and RW(WR) inputs. The DTACK (RDY)

signal is produced by the microport to communicate to the user

that an access has been completed.

DTACK (RDY) goes low

when an internal access is complete and then will return high

after

DS (RD) is deasserted. See the timing diagrams for both

the read and write modes in the specifications.

Input Port Control Registers

The Input Port control register enables various input-related

features used primarily for input detection and level control.

Depending on the mode of operation, up to four different signal

paths can be monitored with these registers. These features are

accessed by setting Bit 5 of external address 3 (Sleep Register)

and then using the CAR (external address 6) to address the

eight available locations.

Response to these settings is directed to the LIA-A, LIA-B,

LIB-A and LIB-B pins.

Address 00 is the lower threshold for Input Channel A. This

word is 10 bits wide and maps to the 10 most significant bits

of the mantissa. If the upper 10 bits are less than or equal to this

value, the lower threshold has been met. In normal chip operation,

this starts the dwell time counter. If the input signal increases

above this value, the counter is reloaded and awaits the input to

drop back to this level.

Address 01 is the upper threshold for Input Channel A. This

word is 10 bits wide and maps to the 10 most significant bits of

the mantissa. If the upper 10 bits are greater than or equal to

this value, the upper threshold has been met. In normal chip

operation, this will cause the appropriate LI pin (LIA–A or

LIA–B) to become active.

Address 02 is the dwell time for Input Channel A. This sets the

time that the input signal must be at or below the lower thresh-

old before the LI pin is deactivated. For the input level detector

to work, the dwell time must be set to at least one. If set to zero,

the LI functions are disabled.

Address 02 has a 20-bit register. When the lower threshold is

met following an excursion into the upper threshold, the dwell

time counter is loaded and begins to count high-speed clock

cycles as long as the input is at or below the lower threshold. If

the signal increases above the lower threshold, the counter is

reloaded and waits for the signal to fall below the lower thresh-

old again.

Address 03 configures Input Channel A.

Bit 4 determines the polarity of LIA-A and LIA-B. If this bit is

cleared, the LI signal is high when the upper threshold has been

exceeded. However, if this bit is set, the LI pin is low when active.

This allows maximum flexibility when using this function.

AD6624S/PCB 数据表(PDF) 35 Page - Analog Devices

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