AD6624SSLASHPCB datasheet(26/40 Pages) AD

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REV. B

AD6624

–26–

SDIV0

SCLK

RFS

SCLK

SDI

SDO

SDFS

SDFE

SBM0

AD6624

DSP

CH 0

10k

Figure 35. Typical Serial Data Output Interface to DSP

(Serial Slave Mode, SBM = 0)

Serial Ports Cascaded

Serial output ports may be cascaded on the AD6624 such that

the SDO’s outputs are shorted together. In this mode, the SDO

port of the master channel three-states when the SDO port of

the slave channel is active. This allows data to be shifted out of

a slave channel immediately following the completion of data

frame (I/Q pair) shifting out of a master AD6624 channel. To

accomplish this, the SDFE signal of the master channel drives

the SDFS input of the slave channel. Serial output port cascad-

ing can be used with channels on the same AD6624 device, or

with channels on two different devices as shown in Figure 36.

To satisfy tSSF and tHSF timing requirements of the slave chan-

nel, the SDFE signal from the master channel should be delayed

using a noninverting buffer (e.g., 74LVC244A) that provides a

minimum of 1.5 ns of propagation delay. Figure 36 shows the

cascade capability between two AD6624 devices. The first is

connected as a serial master (SBM = 1) and the second is con-

figured in Serial Cascade mode (SBM = 0).

Using the AD6624 master/slave mode permits a DSP to shift

the data from the master AD6624 serial port, followed immedi-

ately by a frame of data (I and Q words) from the AD6624 slave

port. As shown in Figure 36, the master port is Serial Port 0. The

slave port can be either Serial Port 1, 2, or 3, or a Serial Port 0

from another AD6624. Other AD6624 serial ports can be cascaded

to the slave port by using the SDFE and SDFS in the manner

shown. The only limit to the number of ports that can be cas-

caded comes from serial bandwidth and fan-out considerations.

There must be enough serial clock cycles available to shift the

necessary data into the DSP, and the SCLK (common to all

channels and DSP) must be closely monitored to ensure that it

is a clean signal. For systems where a single DSP serial port will

be connected to many AD6624 serial ports, it is recommended

that the SCLK signal from the master be buffered to the slaves.

See Serial Port Buffering in the Applications section.

SDIV0

SCLK

RFS

SCLK

SDI

SDO

SDFS

SDFE

SBM0

3.3V

AD6624

DSP

CH 0

MASTER

SCLK

SDI

SDO

SDFS

SDFE

AD6624

CH 0

CASCADE

10k

BUFFER

Figure 36. Typical Serial Data Output Interface to DSP

(Serial Cascade Mode, SBM = 0)

Serial Output Frame Timing (Master and Slave)

The SDFS signal transitions accordingly depending on whether

the part is in Master (SBM = 1, Figure 43) or Slave (SBM = 0,

Figure 32) mode. The next rising edge of SCLK after this occurs

will drive the first bit of the serial data on the SDO pin. The

falling edge of SCLK or the subsequent rising edge can then be

used by the DSP to sample the data until the required number

of bits is received (determined by the serial output port word

length). If the DSP has the ability to count bits, the DSP will

know when the complete frame is received. If not, the DSP can

monitor the SDFE pin to determine that the frame is complete.

Serial Port Timing Specifications

Whether the AD6624 serial channel is operated as a Serial Bus

Master or as a Serial Slave, the serial port timing is identical.

Figures 38 to 44 indicate the required timing for each of the

specifications.

SCLK

tSCLKL

tSCLK

tSCLKH

Figure 37. SCLK Timing Requirements

CLK

SCLK

tDSCLKH

tSCLKH

tSCLKL

Figure 38. SCLK Switching Characteristics (Divide by 1)

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