AD6624SSLASHPCB datasheet(25/40 Pages) AD

25 / 40 page

REV. B

AD6624

–25–

of the frame or it can be used as the SDFS (Serial Data Frame

Sync) of another AD6624 chip or channel running in Serial

Cascade mode.

Serial Data Frame (Serial Cascade)

Any of the AD6624 serial outputs may be operated in the serial

cascade mode (serial slave). In this mode, the selected AD6624

channel requires an external device such as a DSP to issue the

serial clock and SDFS.

To operate successfully in the serial cascade mode, the DSP

must have some indication that the AD6624 channel’s serial

buffer is ready to send data. This is indicated by the assertion of

the DRx pin where “x” is the channel number. This pin should

be tied to an interrupt or flag pin of the DSP. In this manner,

the DSP will know when to service the serial port.

When the DSP begins handling the serial service, the serial port

should be configured such that the SDFS pin is asserted one

clock cycle prior to shifting data. As such, the AD6624 channel

samples the SDFS pin on the rising edge of the serial clock. On

the next rising edge of the serial clock, the AD6624 serial

port begins shifting data until the specified number of bits

has been shifted.

SCLK

SDO

SDFS

I15

I14

tHSF

tSSF

Figure 32. SDO, SDFS Switching Characteristics (SBM = 0)

On the last bit of the serial frame (least significant bit of the Q

word), the SDFE is raised. The SDFE signal can either be used

by the DSP to indicate the end of the frame or it can be used as

the SDFS of another AD6624 chip or channel running in Serial

Cascade mode.

SCLK

SDO

SDFE

tDSDFE

I15

I14

tDSO

Figure 33. SDO, SDFE Switching Characteristics

Configuring the Serial Ports

Each Serial Output Port may function as either a master or

slave. A Serial Bus Master will provide SCLK (SCLK0, SCLK1,

SCLK2, SCLK3) and SDFS outputs. A Serial Slave will accept

these signals as inputs. Upon the lift of

RESET, Serial Port 0

will become a master if the SBM0 pin is high, and a slave if

SBM0 is low. Serial Ports 1, 2, and 3 will always default to serial

slaves when

RESET is taken low. They can be programmed as a

master by setting the SBM1, SBM2, and SBM3 bits in the

0xA9 Registers high.

Serial Port Data Rate

If a Serial Port is defined as a master, the SCLK frequency is

defined by Equation 15. fCLK is the frequency of the master

clock of the AD6624 channel and SDIV is the Serial Division

word for the channel (1, 2, or 3). The SDIV for Serial Port 0

is located directly as pins on the package for easy hardware

configuration and is not mapped into 0xA9. For Serial Ports

1, 2, and 3, the internal register 0xA9 Bits 3–0 define the SDIV

(SDIV0, SDIV1, SDIV2, SDIV3) word.

SDIV

SCLK

CLK

(15)

Serial Port to DSP Interconnection

The AD6624 is very flexible in the manner that the serial ports

can be configured and connected to external devices. Each of

the channels can be independently configured and processed by

different DSPs or all of the channels can be chained together to

form a TDM (time division multiplexed) serial chain. This allows

one DSP to handle all of the channels. Additionally, the chan-

nels can be parceled off in any combination in between.

To configure a channel as a serial bus master, Bit 4 of regis-

ter 0xA9 should be set high. However, as with the SDIV pins,

Channel 0 SBM is not mapped to memory and is instead pinned

out and must be hard-wired as either a master or a slave. Figure 34

shows the typical interconnections between an AD6624 Channel

in Serial Bus Master mode and a DSP.

SDIV0

SCLK

RFS

SCLK

SDI

SDO

SDFS

SDFE

SBM0

3.3V

AD6624

DSP

CH 0

MASTER

10k

Figure 34. Typical Serial Data Output Interface to DSP

(Serial Master Mode, SBM = 1)

Serial Slave Operation

The AD6624 can also be operated as a serial bus slave. In this

configuration, shown in Figure 35, the serial clock provided by the

DSP can be asynchronous with the AD6624 clock and input data.

In this mode, the clock has a maximum frequency of 62.5 MHz

and must be fast enough to read the entire serial frame prior to

the next frame coming available. Since the AD6624 output is

derived (via the Decimation/Interpolation Rates) from its input

sample rate, the output rate can be determined by the user. The

output rate of the AD6624 is given below.

OUT

ADC

CIC

RCF

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