AD9515SLASHPCB datasheet(5/28 Pages) AD

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AD9515

Rev. 0 | Page 5 of 28

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

S0 = 1

Zero Scale Delay Time2

0.56

Zero Scale Variation with Temperature

0.47

ps/°C

Full Scale Time Delay2

11.4

Full Scale Variation with Temperature

−5

ps/°C

Linearity, DNL

0.2

LSB

Linearity, INL

0.2

LSB

1 This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.

2 Incremental delay; does not include propagation delay.

CLOCK OUTPUT PHASE NOISE

CLK input slew rate = 1 V/ns or greater.

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK-TO-LVPECL ADDITIVE PHASE NOISE

CLK = 622.08 MHz, OUT = 622.08 MHz

Divide = 1

@ 10 Hz Offset

−125

dBc/Hz

@ 100 Hz Offset

−132

dBc/Hz

@ 1 kHz Offset

−140

dBc/Hz

@ 10 kHz Offset

−148

dBc/Hz

@ 100 kHz Offset

−153

dBc/Hz

>1 MHz Offset

−154

dBc/Hz

CLK = 622.08 MHz, OUT = 155.52 MHz

Divide = 4

@ 10 Hz Offset

−128

dBc/Hz

@ 100 Hz Offset

−140

dBc/Hz

@ 1 kHz Offset

−148

dBc/Hz

@ 10 kHz Offset

−155

dBc/Hz

@ 100 kHz Offset

−161

dBc/Hz

>1 MHz Offset

−161

dBc/Hz

CLK = 622.08 MHz, OUT = 38.88 MHz

Divide = 16

@ 10 Hz Offset

−135

dBc/Hz

@ 100 Hz Offset

−145

dBc/Hz

@ 1 kHz Offset

−158

dBc/Hz

@ 10 kHz Offset

−165

dBc/Hz

@ 100 kHz Offset

−165

dBc/Hz

>1 MHz Offset

−166

dBc/Hz

CLK = 491.52 MHz, OUT = 61.44 MHz

Divide = 8

@ 10 Hz Offset

−131

dBc/Hz

@ 100 Hz Offset

−142

dBc/Hz

@ 1 kHz Offset

−153

dBc/Hz

@ 10 kHz Offset

−160

dBc/Hz

@ 100 kHz Offset

−165

dBc/Hz

> 1 MHz Offset

−165

dBc/Hz

AD9515/PCB 数据表(PDF) 5 Page - Analog Devices

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AD9515/PCB 数据表(PDF) 5 Page - Analog Devices

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