AD9515

Rev. 0 | Page 13 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

VS

2

CLK

3

CLKB

4

VS

5

SYNCB

6

VREF

7

S10

8

S9

18 OUT1B

19 OUT1

20 VS

21 VS

22 OUT0B

23 OUT0

24 VS

17 VS

TOP VIEW

(Not to Scale)

AD9515

Figure 6. 32-Lead LFCSP Pin Configuration

1

32

8

9

25

24

16

17

THE EXPOSED PADDLE

IS AN ELECTRICAL AND

THERMAL CONNECTION

EXPOSED PAD

(BOTTOM VIEW)

GND

Figure 7. Exposed Paddle

Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to

function properly, the paddle must be soldered to a PCB land that functions as both a heat dissipation path as well as an electrical

ground (analog).

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 4, 17, 20, 21, 24, 26, 29, 30

VS

Power Supply (3.3 V).

2

CLK

Clock Input.

3

CLKB

Complementary Clock Input. Used in conjunction with CLK.

5

SYNCB

Used to Synchronize the Outputs; Active Low Signal.

6

VREF

7 to 16, 25

S0 to S10

Programming Pins. These pins determine the operation of the AD9515; 4-state logic.

18

OUT1B

Complementary LVDS/Inverted CMOS Output. Includes a delay block.

19

OUT1

LVDS/CMOS Output. Includes a delay block.

22

OUT0B

Complementary LVPECL Output.

23

OUT0

LVPECL Output.

27, 28

DNC

Do Not Connect.

31, Exposed Paddle

GND

Ground. The exposed paddle on the back of the chip is also GND.

32

RSET

Current Sets Resistor to Ground. Nominal value = 4.12 kΩ.