AD9515SLASHPCB datasheet(25/28 Pages) AD

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AD9515

Rev. 0 | Page 25 of 28

APPLICATIONS

USING THE AD9515 OUTPUTS FOR ADC CLOCK

APPLICATIONS

Any high speed, analog-to-digital converter (ADC) is extremely

sensitive to the quality of the sampling clock provided by the

user. An ADC can be thought of as a sampling mixer, and any

noise, distortion, or timing jitter on the clock is combined with

the desired signal at the A/D output. Clock integrity require-

ments scale with the analog input frequency and resolution,

with higher analog input frequency applications at ≥14-bit

resolution being the most stringent. The theoretical SNR of an

ADC is limited by the ADC resolution and the jitter on the

sampling clock. Considering an ideal ADC of infinite resolution

where the step size and quantization error can be ignored, the

available SNR can be expressed approximately by

⎥

⎦

⎤

⎢

⎣

⎡

SNR

2π

log

where f is the highest analog frequency being digitized.

is the rms jitter on the sampling clock.

Figure 35 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

fA FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz)

100

110

= 100f

200f

400f

1ps

2ps

10ps

SNR = 20log

πf

ATJ

Figure 35. ENOB and SNR vs. Analog Input Frequency

See Application Notes AN-756 and AN-501 at www.analog.com.

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. (Distributing a single-ended clock on a noisy PCB

can result in coupled noise on the sample clock. Differential

distribution has inherent common-mode rejection that can

provide superior clock performance in a noisy environment.)

The AD9515 features both LVPECL and LVDS outputs that

provide differential clock outputs, which enable clock solutions

that maximize converter SNR performance. The input

requirements of the ADC (differential or single-ended, logic

level, termination) should be considered when selecting the best

clocking/converter solution.

LVPECL CLOCK DISTRIBUTION

The low voltage, positive emitter-coupled, logic (LVPECL)

outputs of the AD9515 provide the lowest jitter clock signals

available from the AD9515. The LVPECL outputs (because they

are open emitter) require a dc termination to bias the output

transistors. The simplified equivalent circuit in Figure 31 shows

the LVPECL output stage.

In most applications, a standard LVPECL far-end termination is

recommended, as shown in Figure 36. The resistor network is

designed to match the transmission line impedance (50 Ω) and

the switching threshold (VS − 1.3 V).

LVPECL

SINGLE-ENDED

(NOT COUPLED)

LVPECL

127

VT = VS – 1.3V

Figure 36. LVPECL Far-End Termination

LVPECL

100

Ω DIFFERENTIAL

(COUPLED)

LVPECL

100

0.1nF

200

Figure 37. LVPECL with Parallel Transmission Line

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