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AD9515/PCB 数据表(PDF) 8 Page - Analog Devices |
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AD9515/PCB 数据表(HTML) 8 Page - Analog Devices |
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8 / 28 page  AD9515 Rev. 0 | Page 8 of 28 Parameter Min Typ Max Unit Test Conditions/Comments CLK = 78.6432 MHz, OUT = 78.6432 MHz Divide = 1 @ 10 Hz Offset −122 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −150 dBc/Hz @ 100 kHz Offset −155 dBc/Hz @ 1 MHz Offset −158 dBc/Hz >10 MHz Offset −160 dBc/Hz CLK = 78.6432 MHz, OUT = 39.3216 MHz Divide = 2 @ 10 Hz Offset −128 dBc/Hz @ 100 Hz Offset −136 dBc/Hz @ 1 kHz Offset −146 dBc/Hz @ 10 kHz Offset −155 dBc/Hz @ 100 kHz Offset −161 dBc/Hz >1 MHz Offset −162 dBc/Hz CLOCK OUTPUT ADDITIVE TIME JITTER Table 5. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER CLK = 622.08 MHz 40 fs rms BW = 12 kHz − 20 MHz (OC-12) LVPECL (OUT0) = 622.08 MHz OUT1 off Divide = 1 CLK = 622.08 MHz 55 fs rms BW = 12 kHz − 20 MHz (OC-3) LVPECL (OUT0) = 155.52 MHz OUT1 off Divide = 4 CLK = 400 MHz 215 fs rms Calculated from SNR of ADC method LVPECL (OUT0) = 100 MHz OUT1 off Divide = 4 CLK = 400 MHz 215 fs rms Calculated from SNR of ADC method LVPECL (OUT0) = 100 MHz Divide = 4 LVDS (OUT1) = 100 MHz Interferer CLK = 400 MHz 225 fs rms Calculated from SNR of ADC method LVPECL (OUT0) = 100 MHz Divide = 4 LVDS (OUT1) = 50 MHz Interferer CLK = 400 MHz 230 fs rms Calculated from SNR of ADC method LVPECL (OUT0) = 100 MHz Divide = 4 CMOS (OUT1) = 50 MHz Interferer LVDS OUTPUT ADDITIVE TIME JITTER Delay off CLK = 400 MHz 300 fs rms Calculated from SNR of ADC method LVDS (OUT1) = 100 MHz OUT0 off Divide = 4 CLK = 400 MHz 350 fs rms Calculated from SNR of ADC method LVDS (OUT1) = 100 MHz OUT0 off Divide = 4 LVPECL (OUT0)= 50 MHz Interferer |
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