AD9927BBCZ datasheet(35/100 Pages) AD

35 / 100 page

AD9927

Rev. 0 | Page 35 of 100

maximum of up to 16 toggle positions. Example timing for the

CONCAT_GRP = 1 feature is shown in Figure 38.

If only two groups are needed (up to eight toggle positions) for

the specified timing, the VPATSELB, VPATSELC, and

VPATSELD registers can be programmed to the same value. If

only three groups are needed, VPATSELC and VPATSELD can

be programmed to the same value. Following this approach

conserves register memory if the four separate V-patterns are

not needed.

Note that when CONCAT_GRP is enabled, the Group A

settings are used only for start position, polarity, length, and

repetitions. All toggle positions for Group A, Group B,

Group C, and Group D are combined together and applied

using the settings in the VSTARTA, VPOL_A, VLENA, and

VREPA registers.

Special Vertical Sequence Alternation (SVSA) Mode

The AD9927 has additional flexibility for combining four

different V-pattern groups in a random sequence that can be

programmed for specific CCD requirements. This mode of

operation allows custom vertical sequences for CCDs that

require more complex vertical timing patterns. For example,

using the special vertical sequence alternation mode, it is

possible to support random pattern concatenation, with

additional support for odd/even line alternation.

Figure 40 illustrates four common and repetitive vertical

pattern segments, A through D, that are derived from the

complete vertical pattern. Figure 41 illustrates how each group

can be concatenated together in an arbitrary order.

To enable the SVSA mode, write the VSEQALT_EN bit,

Address 0x20 Bit [13], equal to 0x01. The location of the

VALTSEL registers is shared with the VPAT registers

for XV24. When SVSA mode is enabled, the VALTSEL register

function is selected.

To create SVSA timing, divide the complete vertical timing

pattern into four common and repetitive segments. Identify the

related segments as VPATA, VPATB, VPATC, or VPATD. Up to

four toggle positions for each segment can be programmed

using the V-pattern registers.

Table 15 shows how the segments are specified using a 2-bit

representation. Each bit from VALTSEL0 and VALTSEL1 are

combined to produce four values, corresponding to patterns A,

B, C, and D.

Table 15. VALTSEL Bit Settings for Even and Odd Lines

Parameter

VALTSEL BIT SETTINGS

VALTSEL0_EVEN

VALTSEL1_EVEN

VALTSEL0_ODD

VALTSEL1_ODD

Resulting pattern for even lines

Resulting pattern for odd lines

When the entire pattern is divided, program VALTSEL0 (even

and odd) [17:0] and VALTSEL1 (even and odd) [17:0] so that

the segments will be concatenated in the desired order. If

separate odd and even lines are not required, set the odd and

even registers to the same value.

Figure 42 illustrates the process of using six vertical pattern

segments that have been concatenated into a small, merged

pattern.

Program the register VREPA_1 to specify the number of

segments that will be concatenated into each merged pattern.

The maximum number of segments that can be concatenated to

create a merged pattern is 18. Program VLENA, VLENB, VLENC,

VLEND to be of equal length. Finally, program HBLK to generate

the proper H-clock timing using the procedure for HBLK Mode 2

described in the HBLK Mode 2 Operation section.

It is important to note that because the FREEZE/RESUME

registers are used to specify the VALTSEL registers, the

VALT_MAP register must be enabled when using the special

VALT mode.

Table 16. VALTSEL Register Locations1

When VSEQALT_EN = 1

VALTSEL0_EVEN [12:0]

VSEQ register FREEZE1 [12:0]

VALTSEL0_EVEN [17:13]

VSEQ register RESUME1 [17:13]

VALTSEL1_EVEN [12:0]

VSEQ register FREEZE2 [12:0]

VALTSEL1_EVEN [17:13]

VSEQ register RESUME2 [17:13]

VALTSEL0_ODD [12:0]

VSEQ register FREEZE3 [12:0]

VALTSEL0_ ODD [17:13]

VSEQ register RESUME3 [17:13]

VALTSEL1_ ODD [12:0]

VSEQ register FREEZE4 [12:0]

VALTSEL1_ ODD [17:13]

VSEQ register RESUME4 [17:13]

1 The VALT_MAP register must be set to 1 to enable the use of VALTSEL

registers.

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