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AD9927

Rev. 0 | Page 16 of 100

HIGH SPEED PRECISION TIMING CORE

The AD9927 generates high speed timing signals using the

flexible Precision Timing core. This core is the foundation for

generating the timing used for both the CCD and the AFE; it

includes the reset gate RG, horizontal drivers H1 to H8, HL,

and SHP/SHD sample clocks. A unique architecture makes it

routine for the system designer to optimize image quality by

providing precise control over the horizontal CCD readout

and the AFE correlated double sampling.

The high speed timing of the AD9927 operates the same

way in either master or slave mode configuration. For more

information on synchronization and pipeline delays, see

the Power-Up Sequence for Master Mode section.

Timing Resolution

The Precision Timing core uses a 1× master clock input as a

reference (CLI). This clock should be the same as the CCD pixel

clock frequency. Figure 16 illustrates how the internal timing

core divides the master clock period into 64 steps or edge

positions. Using a 40 MHz CLI frequency, the edge resolution

of the Precision Timing core is approximately 0.4 ns. If a 1×

system clock is not available, it is possible to use a 2× reference

clock by programming the CLIDIVIDE register (AFE Register

Address 0x0D). The AD9927 then internally divides the CLI

frequency by 2.

The AD9927 includes a master clock output, CLO, which

is the inverse of CLI. This output should be used as a crystal

driver. A crystal can be placed between the CLI and CLO pins

to generate the master clock for the AD9927.

High Speed Clock Programmability

Figure 17 shows when the high speed clocks RG, H1 to H8,

SHP, and SHD are generated. The RG pulse has programmable

rising and falling edges and can be inverted using the polarity

control. Horizontal Clock H1 has programmable rising and

falling edges and polarity control. In HCLK Mode 1, H3, H5,

and H7 are equal to H1 and H2, H4, H6, and H8 are always

inverses of H1.

The edge location registers are each six bits wide, allowing the

selection of all 64 edge locations. Figure 20 shows the default

timing locations for all of the high speed clock signals.

P[0]

P[64] = P[0]

P[16]

P[32]

P[48]

ONE PIXEL

PERIOD

CLI

tCLIDLY

POSITION

NOTES

1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (tCLIDLY).

Figure 16. High Speed Clock Resolution from CLI, Master Clock Input

CCD

SIGNAL

PROGRAMMABLE CLOCK POSITIONS:

1SHP SAMPLE LOCATION.

2SHD SAMPLE LOCATION.

3RG RISING EDGE.

4RG FALLING EDGE.

5H1 RISING EDGE.

6H1 FALLING EDGE.

7HL RISING EDGE.

8HL FALLING EDGE.

H2, H4, H6, H8

H1, H3, H5, H7

Figure 17. High Speed Clock Programmable Locations (HCLKMODE = 001)

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