CLC031VEC datasheet(20/31 Pages) NSC

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Device Operation (Continued)

TABLE 3. Control Register Addresses

Address

Hexadecimal

EDH 0

EDH 1

EDH 2

ANC 0

ANC 1

ANC 2

ANC 3

ANC 4

ANC 5

ANC 6

FORMAT 0

FORMAT 1

TEST 0

VIDEO INFO 0

I/O PIN 0 CONFIG

I/O PIN 1 CONFIG

I/O PIN 2 CONFIG

I/O PIN 3 CONFIG

I/O PIN 4 CONFIG

I/O PIN 5 CONFIG

I/O PIN 6 CONFIG

I/O PIN 7 CONFIG

VIDEO CONTROL 0

VIDEO CONTROL 1

REFERENCE CLOCK

EDH 0 (register 01h)

The EDH Full-Field flags F/F UES, F/F IDA, F/F IDH, F/F

EDA andF/F EDH are defined in SMPTE RP 165. The flags

are updated automatically when the EDH function is enabled

and data is being received.

The EDH ENABLE bit, when set, enables operation of the

EDH generator function during SD operation. The default

condition of this bit is set (ON).

The EDH FORCE bit, when set, causes updated EDH pack-

ets to be inserted in the parallel output data regardless of the

previous condition of EDH checkwords and flags in the input

serial data. This function may be used in situations where

video content has been edited thus making the previous

EDH information invalid. The default condition of this bit is

reset (OFF).

The CRC ERROR bit indicates that errors in either the EDH

checksums (SD) or CRC checkwords (HD) were detected in

the serial input data. This bit is a combined function which

indicates the presence of either EDH errors during SD op-

eration or CRC errors during HD operation.

EDH 1 (register 02h)

The EDH Active Picture flags A/P UES, A/P IDA, A/P IDH,

A/P EDA andA/P EDH are defined in SMPTE RP 165. The

flags are updated automatically when the EDH function is

enabled and data is being received.

Specific types of CRC errors in incoming HD serial data are

reported in the CRC ERROR LUMA and CRC ERROR

CHROMA bits.

The CRC REPLACE bit, when set, causes the CRCs in the

incoming data to be replaced with CRCs calculated by the

CLC031. The bit is normally reset (OFF).

EDH 2 (register 03h)

The EDH Ancilliary Data flags ANC UES, ANC IDA, ANC

IDH, ANC EDA andANC EDH are defined in SMPTE RP

165. The flags are updated automatically when the EDH

function is enabled and data is being received.

The status of EDH flag errors in incoming SD serial data are

reported in the ffFlagError, apFlagError and ancFlagError

bits. Each of these bits is the logical-OR of the correspond-

ing EDH and EDA flags.

ANC 0 (Address 04h)

The V FIFO Depth[2:0] bits control the depth of the video

FIFO which preceeds the parallel output data drivers. The

depth can be set from 0 to 4 stages by writing the corre-

sponding binary code into these bits. For example: to set the

Video FIFO depth at two registers, load 11010XXXXXb into

the ANC 0 control register (where X represents the other

functional bits of this register).

Note: When changing some but not all bits in a register and

to retain unchanged other data previously stored in the

with the new data. Then write the modified data back into the

Flags for ANC FIFO EMPTY, ANC FIFO 90% FULL, ANC

FIFO FULL and ANC FIFO OVERRUN are available in the

configuration and control register set. These flags can also

be assigned as outputs on the multi-function I/O port. ANC

FIFO EMPTY when set indicates that the FIFO contains no

data. ANC FIFO 90% FULL indicates when the FIFO is at

90% of capacity. Since it is virtually impossible for the host

processor to begin extracting data from the FIFO after it has

been flagged as full without the possibility of an overrun

condition occurring, ANC FIFO 90% FULL is used as an

advanced command to the host to begin extracting data from

the FIFO. To be used properly, ANC FIFO 90% FULL should

be assigned as an output on the multi-function I/O port and

monitored by the host system. Otherwise, inadvertent loss of

ancilliary packet data could occur. ANC FIFO FULL when

set indicates that the FIFO registers are completely filled

with data.

The ANC FIFO OVERRUN flag indicates that an attempt to

write data into a full FIFO has occurred. ANC FIFO OVER-

RUN can be reset by reading the bit’s status via the

Ancilliary/Control port. If an overrun occurrs, the status of the

FIFO message tracking will be invalidated. In this event, the

FIFO should be flushed to reset the message tracking point-

ers. Any messages then in the FIFO will be lost.

The ANC Checksum Force bit, under certain conditions,

enables the overwriting of ancilliary data checksums re-

ceived in the data. Calculation and insertion of new ancilliary

data checksums is controlled by the ANC Checksum Force

bit. If a checksum error is detected (calculated and received

checksums do not match) and the ANC Checksum Force

bit is set, the ANC Checksum Error bit is set and a new

checksum is inserted in the ancilliary data replacing the

previous one. If a checksum error is detected and the ANC

Checksum Force bit is not set, the checksum mismatch is

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