CLC031VEC datasheet(29/31 Pages) NSC

29 / 31 page

Application Information (Continued)

The power pins feeding the I/O should have low inductance

connections to the power and ground planes. It is recom-

mended that these connections use at least two vias per

power or ground pin. Short interconnecting traces consistent

with good layout practices and soldering rules must be used.

Sampling or clocking of data by external devices should be

so timed as to take maximum advantage of the steady-state

portion of the parallel output data interval. The CLC031 is

designed so that video data will be stable at the positive-

going transition of V

CLK. Data should not be sampled close

to the data transition intervals associated with the negative-

going clock edge. The specified propagation delay and clock

to data timing parameters must be observed. When data is

being sampled from the video data port together with the

ANC port and/or I/O port, it is recommended that the sam-

pling clocks be synchronized with the video clock, V

CLK,to

minimize possible effects from ground bounce or output

droop on sampled signal levels.

PROCESSING NON-SUPPORTED RASTER FORMATS

The number and type of HD raster formats has proliferated

since the CLC031 was designed. Though not specifically

capable of fully or automatically processing these new for-

mats, the CLC031 may still be capable of deserializing them.

The user is encouraged to experiment with processing these

formats, keeping in mind that the CLC031 has not been

tested to handle formats other than those detailed in Table 4.

Therefore, the results from attempts to process non-

supported formats is not guaranteed. The following guide-

lines concerning device setup are provided to aid the user in

configuring the CLC031 to attempt limited processing of

these other raster formats.

In general, the device is configured to defeat its automatic

format detection function and to limit operation to a general

HD format. (The user should consult Table 4 for guidance on

the format groups similar to the non-supported one to be

processed). Since most non-supported formats are in the

HD group, the CLC031 should be configured to operate in

HD-ONLY mode by setting bit-5 of the FORMAT 0 register

(address 0Bh). Also, the device should be further configured

by loading the FORMAT SET[4:0] bits of this register with the

general HD sub-format code. The complete data word for

this general HD sub-format code with HD-ONLY bit set is

330h. Since this format differs from those in the table, the

EAV/SAV indicators are disabled. Without these indicators,

line numbering and CRC processing are disabled and ANC

data extraction will not function. Output video chroma and

luma data will be word-aligned. Post-processing of the par-

allel data output from the CLC031 will be needed to imple-

ment CRC checking or line number tracking.

USING EXTERNAL VCXO FOR VCLK

The EXTERNAL V

CLK bit of VIDEO CONTROL 0 (register

address 55h) is a special application function which enables

use of an external VCXO as a substitute for the internally

generated V

CLK. Additional circuitry is enabled within the

CLC031 which provides phase-frequency detection and con-

trol voltage output for the VCXO. An external loop filter and

voltage amplifier are required to interface the control voltage

output to the VCXO frequency control input. When this func-

tion is used, the R

BB output function is changed from the

bias supply output to the control voltage output of the phase-

frequency detector. The V

CLK output changes function, be-

coming the input for the VCXO signal.

Figure 7 shows an example using dual VCXOs for V

CLK to

handle both standard and high definition video.

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