CLC031VEC datasheet(28/31 Pages) NSC

28 / 31 page

Pin Descriptions (Continued)

Name

Description

CLK

Parallel Video Data Clock Output

DDPLL

Positive Power Supply Input (2.5V supply, PLL)

SSPLL

Negative Power Supply Input (2.5V supply, PLL)

REF

Current Reference Resistor

SDI Bias Supply Resistor

SSSI

Negative Power Supply Input (3.3V supply, Serial Input)

SDI

Serial Data Complement Input

SDI

Serial Data True Input

DDSI

Positive Power Supply Input (3.3V supply, Serial Input)

SSIO

Negative Power Supply Input (3.3V supply, I/O)

XTALi/EXT CLK

Crystal or External 27MHz Clock Input

XTALo

Crystal (Oscillator Output)

DDD

Positive Power Supply Input (2.5V supply, Digital Logic)

ANC/CTRL

Ancilliary/Control Data Port Function Control Input

RD/WR

Ancilliary/Control Data Port Read/Write Control Input

Note: All LVCMOS inputs have internal pull-down devices except VCLK and ACLK.

Application Information

A typical application circuit for the CLC031 is shown in the

Application Circuit diagram. This circuit demonstrates the

capabilities of the CLC031 and allows its evaluation in a

native configuration. An assembled demonstration board is

available, part number SD131EVK. The board may be or-

dered through any of National’s sales offices. Complete

circuit board layouts and schematics for the SD131EVK are

available on National’s WEB site. For latest availability infor-

mation, please see: www.national.com/appinfo/interface.

PCB LAYOUT AND POWER SYSTEM BYPASS

RECOMMENDATIONS

Circuit board layout and stack-up for the CLC031 should be

designed to provide noise-free power to the device. Good

layout practice also will separate high frequency or high-

level inputs and outputs from low-level inputs to minimize

unwanted stray noise pickup, feedback and interference.

Power system performance may be greatly improved by

using thin dielectrics (4 to 10 mils) for power/ground sand-

wiches. This increases the intrinsic capacitance of the PCB

power system which improves power supply filtering, espe-

cially at high frequencies, and makes the value and place-

ment of external bypass capacitors less critical. External

bypass capacitors should include both RF ceramic and tan-

talum electrolytic types. RF capacitors may use values in the

range 0.01 µF to 0.1 µF. Tantalum capacitors may be in the

range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors

should be at least 5X the power supply voltage being used.

It is recommended practice to use two vias at each power pin

of the CLC031 as well as all RF bypass capacitor terminals.

Dual vias reduce the interconnect inductance by up to half,

thereby extending the effective frequency range of the by-

pass components.

The outer layers of the PCB may be flooded with additional

SS (ground) plane. These planes will improve shielding and

isolation as well as increase the intrinsic capacitance of the

power supply plane system. Naturally, to be effective, these

planes must be tied to the V

SS power supply plane at fre-

quent intervals with vias. Frequent via placement also im-

proves signal integrity on signal transmission lines by pro-

viding short paths for image currents which reduces signal

distortion. The planes should be pulled back from all trans-

mission lines and component mounting pads a distance

equal to the width of the widest transmission line or the

thickness of the dielectric separating the transmission line

from the internal power or ground plane(s) whichever is

greater. Doing so minimizes effects on transmission line

impedances and reduces unwanted parasitic capacitances

at component mounting pads.

In especially noisy power supply environments, such as is

often the case when using switching power supplies, sepa-

rate filtering may be used at the CLC031’s PLL and serial

input power pins. The CLC031 was designed for this situa-

tion. The I/O, digital section, PLL and serial input power

supply feeds are independent (see pinout description table

and pinout drawing for details). Supply filtering may take the

form of L-section or pi-section, L-C filters in series with these

DD inputs. Such filters are available in a single package

from several manufacturers. Device power supplies must be

either sequenced as described in POWER SUPPLIES,

POWER-ON-RESET AND RESET INPUT and ideally should

be applied simultaneously as from a common source.

MAINTAINING OUTPUT DATA INTEGRITY

The way in which the TRS and other video data characters

are specified and are therefore output in parallel form can

result in the simultaneous switching of many of the

CLC031’s CMOS outputs. Such switching can lead to the

production of output high level droop or low level ground

bounce. Given in the specifications, V

OLP is the peak output

LOW voltage or ground bounce and V

OHV is the lowest

output HIGH voltage or output droop that may occur under

dynamic simultaneous output switching conditions. V

OHV

and V

OLP are measured with respect to reference ground.

Careful attention to PCB layout, power pin connections to

the power planes and timing of the output data clocking can

reduce these effects. Consideration must also be given to

the timing allocated to external circuits which sample the

outputs.

The effects of simultaneous output switching on output levels

may be minimized by adopting good PCB layout and data

output timing practices, especially critical at HD data rates.

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