AS8579 datasheet(34/44 Pages) AMSCO

34 / 44 page

Document Feedback

AS8579

Datasheet

• PUBLIC

DS000707

• v4-01 • 2022-Jun-08

│ 33

PGA Value

PGA [2:0] Binary

Read/Write

PGA Gain

PGA_7

111

R/W

2.11

7.2.14

PGA Offset Control I-Channel (Address 0x28/0x38)

The 0x38 command is used to program the offset DACs for the I-channel.

This offset compensates for the parasitic offsets in the sensor system and allows to shift DC operating

point in order to maximize the ADC range. The 0x28 command reads the current values of OFFSET1.

DAC outputs can be set to 256 settings (VREG/256) between GND and VREG. (8-bit)

The Offset DAC is used to change the DC operating point of the ADC input. Increasing the Offset DAC

value one count will decrease the ADC input by 80 counts before the accumulation.

7.2.15

PGA Offset Control Q-Channel (Address 0x29/0x39)

The 0x39 command is used to program the offset DAC for the Q-channel.

This offset compensates for the parasitic offsets in the sensor system and allows to shift DC operating

point in order to maximize the ADC range. The 0x29 command reads the current values of OFFSET2.

DAC outputs can be set to 256 settings (VREG/256) between GND and VREG. (8-bit)

The Offset DAC is used to change the DC operating point of the ADC input. Increasing the Offset DAC

value one count will decrease the ADC input by 80 counts before the accumulation.

7.2.16

ADC Control Register (Address 0x2A/0x3A)

The 0x3A command controls the ADC converter cycles. The 0x2A command reads out the ADCTL

Figure 38:

ADCTL Register Overview

ACCU ACCU

ADC

STATE

ADC

STATE

MSB

LSB

AS8579 数据表(PDF) 34 Page - ams AG

AS8579 数据表(HTML) 34 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载