AS8579 datasheet(35/44 Pages) AMSCO

35 / 44 page

Document Feedback

AS8579

Datasheet

• PUBLIC

DS000707

• v4-01 • 2022-Jun-08

│ 34

Figure 39:

ADC Settings

Name

Bit Number

Read/Write

Description

6:7

R/W

Time selection

ACCU

4:5

R/W

Accumulation setting

2:3

R/W

Clock selection

ADC state

0:1

R/W

ADC state selection

ADCTL [7:6] selects how many MCLK clock cycles are used to define the settling phase for the analog

front end (AFE).

Figure 40:

MCLK Frequency Setting

ADCTL [7:6] Binary

System Settling Time in Periods

Time [µs]

1600 MCLK_p

400

2304 MCLK_p

576

2656 MCLK_p

664

1600 MCLK_p

400

ADCTL [5:4] selects how many samples are accumulated for each I and Q channel. Dependent on

how many samples are calculated the I and Q Data varies between 12 & 14-bit. 4 samples = 12-bit,

8 samples = 13-bit, 16 samples = 14-bit

Figure 41:

Accumulation Samples Setting

ADCTL [5:4] Binary

Number of Samples Calculated for I and Q Channel

ADCTL [3:2] selects the ADC clock frequency.

AS8579 数据表(PDF) 35 Page - ams AG

AS8579 数据表(HTML) 35 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载