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AS8579 数据表(PDF) 36 Page - ams AG |
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AS8579 数据表(HTML) 36 Page - ams AG |
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36 / 44 page ![]() Document Feedback AS8579 Register Description Datasheet • PUBLIC DS000707 • v4-01 • 2022-Jun-08 43 │ 35 Figure 42: ADC Frequency Setting ADCTL [3:2] Binary System Settling Time in Periods ADCLK Frequency [kHz] 00 16 * MCLK_p 250 01 8 * MCLK_p 500 10 4 * MCLK_p 1000 11 16 * MCLK_p 250 ADCTL [1:0] selects the ADC state Figure 43: ADC State ADCTL [1:0] Binary ADC State 00 RESET of DSP and ADC stop 01 Start single conversion 10 Start continuous conversions 11 Stop current conversions Figure 44: ADCTL vs System Timing ADCTL Selected Settings System Timing Settling [7:6] Samples [5:4] Freq [3:2] Settling Time (µs) Number of I/Q Samples ADC I/Q Sample Rate (kHz) Settling Time (µs) ADC Sampling Time (µs) Total Time (µs) 00 00 00 400 4 11.36 400 352 752 00 00 01 400 4 22.73 400 176 576 00 00 10 400 4 45.45 400 88 488 00 01 00 400 8 11.36 400 704 1104 00 01 01 400 8 22.73 400 352 752 00 01 10 400 8 45.45 400 176 576 00 10 00 400 16 11.36 400 1408 1808 |
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