GWIXP425BDT datasheet(91/134 Pages) INTEL

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

Datasheet

March 2005

Document Number: 252479, Revision: 005

5.4.14

Reset DC Parameters

5.5

AC Specifications

5.5.1

Clock Signal Timings

5.5.1.1

Processor Clock Timings

Crystal oscillators require that good system-level design practices be followed for reliable start-up

and oscillation. Please refer to the Intel® IXP42X Product Line of Network Processors and

IXC1100 Control Plane Processor Product Line: Crystal Design Considerations Application Note

(Document Number 305588), and contact Intel for the recommended Intel® IXP42X Product Line

of Network Processors and IXC1100 Control Plane Processor part number optimized for use with

crystal oscillators.

Table 38.

PWRON_RESET_N DC Parameters

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

Notes

VIH

Input-high voltage

1.0

1.3

The input voltage

must not exceed

1.3V or long-term

reliability may be

adversely affected.

VIL

Input-low voltage

0.3

IIL

Input leakage current

0 < VIN <

1.3V

-500

µA

CIN

Input Capacitance

Simulated results.

Table 39.

Device Clock Timings (Oscillator Reference) (Sheet 1 of 2)

Symbol

Parameter

Min.

Nom.

Max.

Units

Notes

VIH

Input-high voltage

2.0

VIL

Input-low voltage

0.8

TFREQUENCY

Clock frequency for IXP42X product line

and IXC1100 control plane processors

crystal or oscillator.

33.33

MHz

1, 4

FREQUENCY

Clock tolerance over -40º C to 85º C.

-50

ppm

CIN

Pin capacitance of IXP42X product line and

IXC1100 control plane processors’ inputs.

5pF

CSHUNT

CSHUNT is a crystal parameter sometimes

referred to as the holder capacitance.

Notes:

This value could be an oscillator input or a series resonant frequency from a crystal. If used as an

oscillator input, tie to the crystal input pin and leave the crystal output pin disconnected.

Use the component values recommended by the crystal manufacturer.

This parameter applies when driving the clock input with an oscillator.

Where the IXP42X product line or IXC1100 control plane processor is configured with an input

reference-clock, the slew rate should never be faster than 2.5 V/nS to ensure proper PLL operation.

To help ensure proper PLL operation at the slower slew rate, the VIH and VIL voltage levels need to

be within the specified range at an input clock frequency of 33.33 MHz.

GWIXP425BDT 数据表(PDF) 91 Page - Intel Corporation

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