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GWIXP425BDT 数据表(PDF) 45 Page - Intel Corporation |
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GWIXP425BDT 数据表(HTML) 45 Page - Intel Corporation |
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45 / 134 page  Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet March 2005 Document Number: 252479, Revision: 005 45 Table 13. UART Interfaces Name Power On Reset1 Reset2 Type† Description RXDATA0 Z VI I UART serial data input to High-Speed UART Pins. Should be pulled low through a 10-K Ω resistor when not being utilized in the system. TXDATA0 Z VO O UART serial data output. The TXD signal is set to the MARKING (logic 1) state upon a reset operation. High-Speed Serial UART Pins. CTS0_N H VI/PE I UART CLEAR-TO-SEND input to High-Speed UART Pins. When logic 0, this pin indicates that the modem or data set connected to the UART interface of the processor is ready to exchange data. The CTS_N signal is a modem status input whose condition can be tested by the processor. Should be pulled high through a 10-K Ω resistor when not being utilized in the system. RTS0_N H VO/PE O UART REQUEST-TO-SEND output: When logic 0, this informs the modem or the data set connected to the UART interface of the processor that the UART is ready to exchange data. A reset sets the request to send signal to logic 1. LOOP-mode operation holds this signal in its inactive state (logic 1). High-Speed UART Pins. RXDATA1 Z VI I UART serial data input. Should be pulled low through a 10-K Ω resistor when not being utilized in the system. TXDATA1 Z VO O UART serial data output. The TXD signal is set to the MARKING (logic 1) state upon a Reset operation. Console UART Pins. CTS1_N H VI/PE I UART CLEAR-TO-SEND input to Console UART pins. When logic 0, this pin indicates that the modem or data set connected to the UART interface of the processor is ready to exchange data. The CTS_N signal is a modem status input whose condition can be tested by the processor. Should be pulled high through a 10-K Ω resistor when not being utilized in the system. RTS1_N H VO/PE O UART REQUEST-TO-SEND output: When logic 0, this informs the modem or the data set connected to the UART interface of the processor that the UART is ready to exchange data. A reset sets the request to send signal to logic 1. LOOP-mode operation holds this signal in its inactive state (logic 1). Console UART Pins. 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † For a legend of the Type codes, see Table 5 on page 33. |
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