GWIXP425BDT datasheet(97/134 Pages) INTEL

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

Datasheet

March 2005

Document Number: 252479, Revision: 005

5.5.2.3

UTOPIA-2

Figure 18.

UTOPIA-2 Input Timings

Table 46.

UTOPIA-2 Input Timings Values

Symbol

Parameter

Min.

Max.

Units

Notes

Tsetup

Input setup prior to rising edge of clock. Inputs

included in this timing are UTP_IP_DATA[7:0],

UTP_IP_SOC, AND UTP_IP_FCI, and

UTP_OP_FCI.

8ns

Thold

Input hold time after the rising edge of the clock.

Inputs included in this timing are

UTP_IP_DATA[7:0], UTP_IP_SOC, and

UTP_IP_FCI, and UTP_OP_FCI.

1ns

Figure 19.

UTOPIA-2 Output Timings

Table 47.

UTOPIA-2 Output Timings Values

Symbol

Parameter

Min.

Max.

Units

Notes

Tclk2out

Rising edge of clock to signal output. Outputs

included in this timing are UTP_IP_DATA[3:0],

UTP_OP_SOC, UTP_OP_FCO, UTP_IP_FCO,

UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0].

Tholdout

Signal output hold time after the rising edge of

the clock. Outputs included in this timing are

UTP_IP_DATA[3:0], UTP_OP_SOC,

UTP_OP_FCO, UTP_IP_FCO,

UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0].

1ns

Note:

Timing was tested with a 70-pF capacitor to ground.

A9578-01

Thold

Tsetup

Clock

Signals

A9579-01

Tclk2out

Tholdout

Clock

Signals

GWIXP425BDT 数据表(PDF) 97 Page - Intel Corporation

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