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GWIXP425BDT 数据表(PDF) 104 Page - Intel Corporation |
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GWIXP425BDT 数据表(HTML) 104 Page - Intel Corporation |
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104 / 134 page ![]() Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor March 2005 Datasheet 104 Document Number: 252479, Revision: 005 Table 54. Intel® Multiplexed Mode Values Symbol Parameter Min. Max. Units Notes Talepulse Pulse width of EX_ALE (ADDR is valid at the rising edge of EX_ALE) 141 Cycles 1, 7 Tale2addrhold Valid address hold time after from falling edge of EX_ALE 1 1 Cycles 1, 2, 7 Tdval2valwrt Write data valid prior to EX_WR_N falling edge 1 4 Cycles 3, 7 Twrpulse Pulse width of the EX_WR_N 1 16 Cycles 4, 7 Tdholdafterwr Valid data after the rising edge of EX_WR_N 1 4 Cycles 5, 7 Tale2valcs Valid chip select after the falling edge of EX_ALE 1 4 Cycles 7 Trdsetup Data valid required before the rising edge of EX_RD_N 15 ns Trdhold Data hold required after the rising edge of EX_RD_N 0 ns Trecov Time needed between successive accesses on expansion interface. 116 Cycles 6 Notes: 1. The EX_ALE signal is extended from 1 to 4 cycles based on the programming of the T1 timing parameter. The parameter Tale2addrhold is fixed at 1 cycle. 2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device. 3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or write) to an external device. Data will be available during this time as well. 5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the expansion interface. 7. One cycle is the period of the Expansion Bus clock. 8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. Timing tests were performed with a 70-pF capacitor to ground. |
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