GWIXP425BBT datasheet(98/134 Pages) INTEL

部件名	GWIXP425BBT

功能描述	Intel짰 IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

PDF	134 Pages

Scroll/Zoom	100%

制造商	INTEL [Intel Corporation]

网页	http://www.intel.com

标志

98 / 134 page

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

March 2005

Datasheet

Document Number: 252479, Revision: 005

5.5.2.4

MII

Figure 20.

MII Output Timings

Table 48.

MII Output Timings Values

Symbol

Parameter

Min.

Max.

Units

Notes

Clock to output delay for ETH_TXDATA and

ETH_TXEN.

017

ETH_TXDATA and ETH_TXEN hold time after

ETH_TXCLK.

Note:

These values satisfy the MII specification requirement of 0 ns to 25 ns clock to output delay.

Figure 21.

MII Input Timings

Table 49.

MII Input Timings Values

Symbol

Parameter

Min.

Max.

Units

Notes

ETH_RXDATA and ETH_RXDV setup time prior

to rising edge of ETH_RXCLK

5.5

1, 2

ETH_RXDATA and ETH_RXDV hold time after

the rising edge of ETH_RXCLK

1, 2, 3

Notes:

These values satisfy the MII specification requirement of 10-ns setup and hold time.

Timing tests were performed with a 70-pF capacitor to ground.

This parameter has been simulated but has not been fully tested.

A9580-01

eth_tx_clk

eth_tx_data[7:0]

eth_tx_en

eth_crs

A9581-01

eth_rx_clk

eth_rx_data[7:0]

eth_rx_dv

eth_crs

GWIXP425BBT 数据表(PDF) 98 Page - Intel Corporation

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