GWIXP425BBT datasheet(38/134 Pages) INTEL

38 / 134 page

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

March 2005

Datasheet

Document Number: 252479, Revision: 005

Table 8.

High-Speed, Serial Interface 0

Name

Power

Reset1

Reset2

Type†

Description

HSS_TXFRAME0

I/O

The High-Speed Serial (HSS) transmit frame signal can be

configured as an input or an output to allow an external

source become synchronized with the transmitted data. Often

known as a Frame Sync signal. Configured as an input upon

reset.

Should be pulled low with a 10-K

Ω resistor when not being

utilized in the system.

HSS_TXDATA0

O/D

Transmit data out. Open Drain output.

Must be pulled high with a 10-K

Ω resistor to V

CCP.

HSS_TXCLK0

I/O

The High-Speed Serial (HSS) transmit clock signal can be

configured as an input or an output. The clock can be a

frequency ranging from 512 KHz to 8.192 MHz. Used to clock

out the transmitted data. Configured as an input upon reset.

Frame sync and data can be selected to be generated on the

rising or falling edge of the transmit clock.

Should be pulled low with a 10-K

Ω resistor when not being

utilized in the system.

HSS_RXFRAME0

I/O

The High-Speed Serial (HSS) receive frame signal can be

configured as an input or an output to allow an external

source to become synchronized with the received data. Often

known as a Frame Sync signal. Configured as an input upon

reset.

Should be pulled low with a 10-K

Ω resistor when not being

utilized in the system.

HSS_RXDATA0

Receive data input. Can be sampled on the rising or falling

edge of the receive clock.

Should be pulled low through a 10-K

Ω resistor when not

being utilized in the system.

HSS_RXCLK0

I/O

The High-Speed Serial (HSS) receive clock signal can be

configured as an input or an output. The clock can be from

512 KHz to 8.192 MHz. Used to sample the received data.

Configured as an input upon reset.

Should be pulled low with a 10-K

Ω resistor when not being

utilized in the system.

While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.

After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of

PLL_LOCK, all signals reflect the value shown in the RESET column.

†

For a legend of the Type codes, see Table 5 on page 33.

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