GWIXP425BBT datasheet(37/134 Pages) INTEL

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

Datasheet

March 2005

Document Number: 252479, Revision: 005

PCI_DEVSEL_N

I/O

PCI Device Select:

•

When used as an output, PCI_DEVSEL_N indicates that

device has decoded that address as the target of the

requested transaction.

•

When used as an input, PCI_DEVSEL_N indicates if any

device on the PCI bus exists with the given address.

Should be pulled high with a 10-K

Ω resistor when not being

utilized in the system.

PCI_IDSEL

PCI Initialization Device Select is a chip select during

configuration reads and writes.

Should be pulled high with a 10-K

Ω resistor when not being

utilized in the system.

PCI_REQ_N[3:1]

PCI arbitration request: Used by the internal PCI arbiter to allow

an agent to request the PCI bus.

Should be pulled high with a 10-K

Ω resistor when not being

utilized in the system.

PCI_REQ_N[0]

I/O

PCI arbitration request:

•

When configured as an input (PCI arbiter enabled), the

internal PCI arbiter will allow an agent to request the PCI

bus.

•

When configured as an output (PCI arbiter disabled), the pin

will be used to request access to the PCI bus from an

external arbiter.

Should be pulled high with a 10-K

Ω resistor, when the PCI bus is

not being utilized in the system.

PCI_GNT_N[3:1]

PCI arbitration grant: Generated by the internal PCI arbiter to

allow an agent to claim control of the PCI bus.

PCI_GNT_N[0]

I/O

PCI arbitration grant:

•

When configured as an output (PCI arbiter enabled), the

internal PCI arbiter to allow an agent to claim control of the

PCI bus.

•

When configured as an input (PCI arbiter disabled), the pin

will be used to claim access of the PCI bus from an external

arbiter.

Should be pulled high with a 10-K

Ω resistor when not being

utilized in the system.

PCI_INTA_N

O/D

PCI interrupt: Used to request an interrupt.

Should be pulled high with a 10-K

Ω resistor when not being

utilized in the system.

PCI_CLKIN

PCI Clock: provides timing for all transactions on PCI. All PCI

signals — except INTA#, INTB#, INTC#, and INTD# — are

sampled on the rising edge of CLK and timing parameters are

defined with respect to this edge. The PCI clock rate can operate

at up to 66 MHz.

Should be pulled low with a 10-K

Ω resistor when not being

utilized in the system.

Table 7.

PCI Controller (Sheet 2 of 2)

Name

Power

Reset1

Reset2 Type†

Description

While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.

After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of

PLL_LOCK, all signals reflect the value shown in the RESET column.

†

For a legend of the Type codes, see Table 5 on page 33.

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