GWIXP425BBT datasheet(34/134 Pages) INTEL

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

March 2005

Datasheet

Document Number: 252479, Revision: 005

• Table 8 — High-Speed, Serial Interface 0 signals

• Table 9 — High-Speed, Serial Interface 1 signals

• Table 10 — MII Interfaces signals

• Table 11 — UTOPIA-2 Interface signals

• Table 12 — Expansion Bus Interface signals

• Table 13 — UART Interfaces signals

• Table 14 — USB Interface signals

• Table 15 — Oscillator Interface signals

• Table 16 — GPIO Interface signals

• Table 17 — JTAG Interface signals

• Table 18 — System Interface†† signals

• Table 19 — Power Interface signals

Table 6.

SDRAM Interface (Sheet 1 of 2)

Name

Power

Reset1

Reset2

Type†

Description

SDM_ADDR[12:0]

SDRAM Address: A0-A12 signals are output during the

READ/WRITE commands and ACTIVE commands to select a

location in memory to act upon.

SDM_DATA[31:0]

I/O

SDRAM Data: Bidirectional data bus used to transfer data to

and from the SDRAM

SDM_CLKOUT

SDRAM Clock: All SDRAM input signals are sampled on the

rising edge of SDM_CLKOUT. All output signals are driven

with respect to the rising edge of SDM_CLKOUT.

SDM_BA[1:0]

SDRAM Bank Address: SDM_BA0 and SDM_BA1 define the

bank the current command is attempting to access.

SDM_RAS_N

SDRAM Row Address strobe/select (active low): Along with

SDM_CAS_N, SDM_WE_N, and SDM_CS_N signals

determines the current command to be executed.

SDM_CAS_N

SDRAM Column Address strobe/select (active low): Along

with SDM_RAS_N, SDM_WE_N, and SDM_CS_N signals

determines the current command to be executed.

SDM_CS_N[1:0]

SDRAM Chip select (active low): CS# enables the command

decoder in the external SDRAM when logic low and disables

the command decoder in the external SDRAM when logic

high.

SDM_WE_N

SDRAM Write enable (active low): Along with SDM_CAS_N,

SDM_RAS_N, and SDM_CS_N signals determines the

current command to be executed.

While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.

After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of

PLL_LOCK, all signals reflect the value shown in the RESET column.

†

For a legend of the Type codes, see Table 5 on page 33.

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